HV-haptics module with V2 revision supports 640 bytes FIFO memory and
each byte contains a FIFO sample. There are 4 adjacent SPMI registers
which can be used for filling 4 FIFO samples together by using SPMI
burst writes and also a single register for filling FIFO samples while
the samples are less than 4.
Also update the logic of writing FIFO samples: Check the available
FIFO memory first and then write FIFO with samples no more than the
available FIFO memory space. With this new logic, it's not necessory
to read FIFO_READY_STS register before writing FIFO samples and this
helps on reducing FIFO writing latency.
Change-Id: If65a81327dfd2c6af0d58055c0ae93ad6c1dcba0
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
43e9761748