mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
e633522ef7
Add VADC and ADCTM channels with corresponding thermal zones for ADC thermistors under PMD9650 on sdxnightjar. Change-Id: I1fa2d9ad2a3eaaf0c3c250d671fb297e520095c6
110 lines
2.3 KiB
Devicetree
110 lines
2.3 KiB
Devicetree
#include <dt-bindings/input/input.h>
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#include <dt-bindings/input/qcom,qpnp-power-on.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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&spmi_bus {
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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qcom,pmd9650@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmd9650_pon: qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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qcom,pon-dbc-delay = <15625>;
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interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>;
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interrupt-names = "kpdpwr";
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qcom,system-reset;
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qcom,store-hard-reset-reason;
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qcom,use-legacy-hard-reset-offset;
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qcom,pon_1 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
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qcom,pull-up;
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linux,code = <KEY_POWER>;
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};
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};
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pmd9650_gpios: pinctrl@c000 {
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compatible = "qcom,pmd9650-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pmd9650_vadc: vadc@3100 {
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compatible = "qcom,spmi-adc-rev2";
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reg = <0x3100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eoc-int-en-set";
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#io-channel-cells = <1>;
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io-channel-ranges;
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die_temp {
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reg = <ADC5_DIE_TEMP>;
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label = "die_temp";
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qcom,pre-scaling = <1 1>;
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};
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ref_gnd {
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reg = <ADC5_REF_GND>;
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label = "ref_gnd";
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qcom,pre-scaling = <1 1>;
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};
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ref_1p25 {
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reg = <ADC5_1P25VREF>;
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label = "ref_1p25";
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qcom,pre-scaling = <1 1>;
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};
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xo_therm {
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reg = <ADC5_XO_THERM_100K_PU>;
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label = "xo_therm";
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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};
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};
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qcom,pmd9650_rtc {
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compatible = "qcom,pm8941-rtc";
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interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
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};
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};
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qcom,pmd9650@1 {
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compatible = "qcom,spmi-pmic";
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reg = <1 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pmd9650_pwm_1: pwm@bc00 {
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compatible = "qcom,pwm-lpg";
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reg = <0xbc00>;
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reg-names = "lpg-base";
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#pwm-cells = <2>;
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qcom,num-lpg-channels = <1>;
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};
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pmd9650_pwm_2: pwm@bd00 {
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compatible = "qcom,pwm-lpg";
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reg = <0xbd00>;
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reg-names = "lpg-base";
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#pwm-cells = <2>;
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qcom,num-lpg-channels = <1>;
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};
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};
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};
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