This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Andrew Lunn <[email protected]>
Tested-by Gregory CLEMENT <[email protected]>
97fa4cf442