mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-15 01:01:56 -04:00
d58562d66e
Enable L3 interconnect driver so that consumers are able to obtain their path handles properly. Change-Id: I99a5085192c1d551e5d0973bb50f96d27d97746a
1466 lines
31 KiB
Devicetree
1466 lines
31 KiB
Devicetree
#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,camcc-scshrike.h>
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#include <dt-bindings/clock/qcom,dispcc-scshrike.h>
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#include <dt-bindings/clock/qcom,gcc-scshrike.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
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#include <dt-bindings/clock/qcom,npucc-sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,scshrike.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDMSHRIKE";
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compatible = "qcom,sdmshrike";
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qcom,msm-name = "SDMSHRIKE";
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qcom,msm-id = <340 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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serial0 = &uart2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x400000>;
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cache-level = <3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_1>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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#cooling-cells = <2>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_2>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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#cooling-cells = <2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_200: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_200: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_3>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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#cooling-cells = <2>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_300: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_300: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_4>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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#cooling-cells = <2>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_5>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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#cooling-cells = <2>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_6>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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#cooling-cells = <2>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_7>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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#cooling-cells = <2>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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firmware: firmware {
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp_mem@85700000 {
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no-map;
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@85e00000 {
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no-map;
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reg = <0x0 0x85e00000 0x0 0x140000>;
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};
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flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
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no-map;
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reg = <0x0 0x85ffd000 0x0 0x3000>;
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};
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aop_cmd_db: memory@85f20000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x85f20000 0x0 0x20000>;
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no-map;
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};
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smem_region: smem@86000000 {
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no-map;
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reg = <0x0 0x86000000 0x0 0x200000>;
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};
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removed_regions: removed_regions@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x5500000>;
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};
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pil_camera_mem: camera_region@8b700000 {
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no-map;
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reg = <0x0 0x8b700000 0x0 0x500000>;
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};
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pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
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no-map;
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reg = <0x0 0x8bc00000 0x0 0x180000>;
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};
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pil_npu_mem: pil_npu_region@0x8bd80000 {
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no-map;
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reg = <0x0 0x8bd80000 0x0 0x80000>;
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};
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pil_adsp_mem: pil_adsp_region@0x8be00000 {
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no-map;
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reg = <0x0 0x8be00000 0x0 0x1a00000>;
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};
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pil_modem_mem: modem_region@0x8d800000 {
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no-map;
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reg = <0x0 0x8d800000 0x0 0x9600000>;
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};
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pil_video_mem: pil_video_region@0x96e00000 {
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no-map;
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reg = <0x0 0x96e00000 0x0 0x500000>;
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};
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pil_slpi_mem: pil_slpi_region@0x97300000 {
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no-map;
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reg = <0x0 0x97300000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 {
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no-map;
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reg = <0x0 0x98700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 {
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no-map;
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reg = <0x0 0x98710000 0x0 0x5000>;
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};
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pil_gpu_mem: pil_gpu_region@0x98715000 {
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no-map;
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reg = <0x0 0x98715000 0x0 0x2000>;
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};
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pil_spss_mem: pil_spss_region@0x98800000 {
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no-map;
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reg = <0x0 0x98800000 0x0 0x100000>;
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};
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pil_cdsp_mem: cdsp_regions@0x98900000 {
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no-map;
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reg = <0x0 0x98900000 0x0 0x1400000>;
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};
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qseecom_mem: qseecom_region@0x9e400000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0x9e400000 0x0 0x1400000>;
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};
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cont_splash_memory: cont_splash_region@0x9c000000 {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "cont_splash_region";
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};
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disp_rdump_memory: disp_rdump_region@0x9c000000 {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "disp_rdump_region";
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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cdsp_mem: cdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x800000>;
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};
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secure_display_memory: secure_display_region { /* Secure UI */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xA000000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x2400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2800000>;
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linux,cma-default;
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};
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};
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vendor: vendor {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <1 9 4>;
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interrupt-parent = <&intc>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sm8150-pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 1 0xf08>,
|
|
<1 2 0xf08>,
|
|
<1 3 0xf08>,
|
|
<1 0 0xf08>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
timer@0x17c20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c20000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@0x17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <0 7 0x4>,
|
|
<0 6 0x4>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <0 8 0x4>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <0 9 0x4>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <0 10 0x4>;
|
|
reg = <0x17c26000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <0 11 0x4>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <0 12 0x4>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <0 13 0x4>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
};
|
|
};
|
|
|
|
qcom,msm-imem@146bf000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146bf000 0x1000>;
|
|
ranges = <0x0 0x146bf000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>;
|
|
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8150-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
system_pm {
|
|
compatible = "qcom,system-pm";
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-config = <SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<ACTIVE_TCS 2>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
disp_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
|
|
};
|
|
};
|
|
|
|
osm_l3: interconnect@18321000 {
|
|
reg = <0x18321000 0x1400>;
|
|
compatible = "qcom,scshrike-osm-l3";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
reg = <0x1500000 0x7400>;
|
|
compatible = "qcom,scshrike-config_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
reg = <0x1620000 0x29400>;
|
|
compatible = "qcom,scshrike-system_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
ipa_virt: interconnect@0 {
|
|
compatible = "qcom,scshrike-ipa_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
camnoc_virt: interconnect@1 {
|
|
compatible = "qcom,scshrike-camnoc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
reg = <0x16E0000 0x1A080>;
|
|
compatible = "qcom,scshrike-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
reg = <0x1700000 0x3A080>;
|
|
compatible = "qcom,scshrike-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnet@1740000 {
|
|
reg = <0x1740000 0x1C100>;
|
|
compatible = "qcom,scshrike-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect@9160000 {
|
|
reg = <0x9160000 0x3200>;
|
|
compatible = "qcom,scshrike-dc_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@9680000 {
|
|
reg = <0x9680000 0x3E200>;
|
|
compatible = "qcom,scshrike-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect@2 {
|
|
compatible = "qcom,scshrike-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
compute_noc: interconnect@9800000 {
|
|
reg = <0x9800000 0x40000>;
|
|
compatible = "qcom,scshrike-compute_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
|
|
reg-names = "msgram", "irq-reg-base";
|
|
qcom,irq-mask = <0x1>;
|
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "aop";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aopcc: qcom,aopcc@0 {
|
|
compatible = "qcom,aop-qmp-clk";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "qdss_clk";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,scshrike-gcc", "syscon";
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
clock-names =
|
|
"bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
scc: clock-controller@2b10000 {
|
|
compatible = "qcom,sa8195-scc";
|
|
reg = <0x2b10000 0x30000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpucc: clock-controller@2c90000 {
|
|
compatible = "qcom,scshrike-gpucc", "syscon";
|
|
reg = <0x2c90000 0x9000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gcc_gpu_gpll0_clk_src",
|
|
"gcc_gpu_gpll0_div_clk_src";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
npucc: clock-controller@9910000 {
|
|
compatible = "qcom,sm8150-npucc", "syscon";
|
|
reg = <0x9910000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_gdsc-supply = <&npu_core_gdsc>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
|
|
<&gcc GCC_NPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_NPU_AXI_CLK>;
|
|
clock-names =
|
|
"bi_tcxo",
|
|
"gcc_npu_gpll0_div_clk_src",
|
|
"gcc_npu_gpll0_clk_src",
|
|
"gcc_npu_axi_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@ab00000 {
|
|
compatible = "qcom,sm8150-videocc", "syscon";
|
|
reg = <0xab00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names =
|
|
"cfg_ahb_clk",
|
|
"bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ad00000 {
|
|
compatible = "qcom,scshrike-camcc", "syscon";
|
|
reg = <0xad00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>;
|
|
clock-names =
|
|
"cfg_ahb_clk",
|
|
"bi_tcxo",
|
|
"sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,scshrike-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-names = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>;
|
|
clock-names =
|
|
"cfg_ahb_clk",
|
|
"bi_tcxo",
|
|
"sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apsscc: syscon@182a0000 {
|
|
compatible = "syscon";
|
|
reg = <0x182a0000 0x1c>;
|
|
};
|
|
|
|
mccc: syscon@90b0000 {
|
|
compatible = "syscon";
|
|
reg = <0x90b0000 0x54>;
|
|
};
|
|
|
|
debugcc: debug-clock-controller@0 {
|
|
compatible = "qcom,scshrike-debugcc";
|
|
qcom,gcc = <&gcc>;
|
|
qcom,videocc = <&videocc>;
|
|
qcom,camcc = <&camcc>;
|
|
qcom,dispcc = <&dispcc>;
|
|
qcom,npucc = <&npucc>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,apsscc = <&apsscc>;
|
|
qcom,mccc = <&mccc>;
|
|
clock-names = "xo_clk_src";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18323000 {
|
|
compatible = "qcom,cpufreq-hw";
|
|
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#freq-domain-cells = <2>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem@8600000 {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_region>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
apcs: syscon@17c0000c {
|
|
compatible = "syscon";
|
|
reg = <0x17c0000c 0x4>;
|
|
};
|
|
|
|
apss_shared: mailbox@17c00000 {
|
|
compatible = "qcom,sm8150-apss-shared";
|
|
reg = <0x17c00000 0x1000>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
sp_scsr: mailbox@188501c {
|
|
compatible = "qcom,sm8150-spcs-global";
|
|
reg = <0x188501c 0x4>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
sp_scsr_block: syscon@1880000 {
|
|
compatible = "syscon";
|
|
reg = <0x1880000 0x10000>;
|
|
};
|
|
|
|
intsp: qcom,qsee_irq {
|
|
compatible = "qcom,sm8150-qsee-irq";
|
|
|
|
syscon = <&sp_scsr_block>;
|
|
interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 349 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "sp_ipc0",
|
|
"sp_ipc1";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
qcom,qsee_irq_bridge {
|
|
compatible = "qcom,qsee-ipc-irq-bridge";
|
|
|
|
qcom,qsee-ipc-irq-spss {
|
|
qcom,dev-name = "qsee_ipc_irq_spss";
|
|
label = "spss";
|
|
interrupt-parent = <&intsp>;
|
|
interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&apss_shared 12>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,modem_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_adsp>,
|
|
<&glink_slpi>,
|
|
<&glink_cdsp>,
|
|
<&glink_spss>;
|
|
};
|
|
};
|
|
|
|
glink_adsp: adsp {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&apss_shared 8>;
|
|
mbox-names = "adsp_smem";
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
cpu-affinity = <1 2>;
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,apr_tal_rpmsg {
|
|
qcom,glink-channels = "apr_audio_svc";
|
|
qcom,intents = <0x200 20>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,adsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>,
|
|
<&glink_slpi>,
|
|
<&glink_cdsp>;
|
|
};
|
|
};
|
|
|
|
glink_slpi: dsps {
|
|
qcom,remote-pid = <3>;
|
|
transport = "smem";
|
|
mboxes = <&apss_shared 24>;
|
|
mbox-names = "dsps_smem";
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "slpi";
|
|
qcom,glink-label = "dsps";
|
|
|
|
qcom,slpi_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,slpi_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>,
|
|
<&glink_adsp>,
|
|
<&glink_cdsp>;
|
|
};
|
|
};
|
|
|
|
glink_cdsp: cdsp {
|
|
qcom,remote-pid = <5>;
|
|
transport = "smem";
|
|
mboxes = <&apss_shared 4>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,cdsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>,
|
|
<&glink_adsp>,
|
|
<&glink_slpi>;
|
|
};
|
|
};
|
|
|
|
glink_spss: spss {
|
|
qcom,remote-pid = <8>;
|
|
transport = "spss";
|
|
mboxes = <&sp_scsr 0>;
|
|
mbox-names = "spss_spss";
|
|
interrupt-parent = <&intsp>;
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
reg = <0x1885008 0x8>,
|
|
<0x1885010 0x4>;
|
|
reg-names = "qcom,spss-addr",
|
|
"qcom,spss-size";
|
|
|
|
label = "spss";
|
|
qcom,glink-label = "spss";
|
|
|
|
qcom,spss_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>;
|
|
};
|
|
};
|
|
|
|
glink_spi_xprt_wdsp: wdsp {
|
|
qcom,remote-pid = <10>;
|
|
transport = "spi";
|
|
tx-descriptors = <0x12000 0x12004>;
|
|
rx-descriptors = <0x1200c 0x12010>;
|
|
|
|
label = "wdsp";
|
|
qcom,glink-label = "wdsp";
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x00ac0000 0x6000>;
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
|
|
uart2: serial@a90000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0x0 0x00a90000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "ok"
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
#include "sdmshrike-pinctrl.dtsi"
|
|
#include "sa8195-regulator.dtsi"
|
|
#include "sm8150-pm.dtsi"
|
|
#include "sa8195-smp2p.dtsi"
|
|
#include "sa8195-gdsc.dtsi"
|
|
|
|
&emac_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&pcie_0_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&pcie_1_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&pcie_2_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&pcie_3_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&ufs_card_2_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&ufs_card_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&ufs_phy_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&usb30_mp_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&usb30_prim_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&usb30_sec_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&bps_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&ife_0_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok"
|
|
};
|
|
|
|
&ife_1_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok"
|
|
};
|
|
|
|
&ife_2_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok"
|
|
};
|
|
|
|
&ife_3_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok"
|
|
};
|
|
|
|
&ipe_0_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&ipe_1_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&titan_top_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok"
|
|
};
|
|
|
|
&mdss_core_gdsc {
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
status = "ok"
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
parent-supply = <&VDD_GFX_LEVEL>;
|
|
status = "ok"
|
|
};
|
|
|
|
&npu_core_gdsc {
|
|
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
status = "ok"
|
|
};
|
|
|
|
&mvs0_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&mvs1_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&mvsc_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok"
|
|
};
|