mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
d930742b8a
Add i2c, spi, uart, common driver and gsi dtsi nodes for monaco. Change-Id: If1ce82a647e4302f0162b1c17507721c19157da9
481 lines
14 KiB
Devicetree
481 lines
14 KiB
Devicetree
#include <dt-bindings/interconnect/qcom,monaco.h>
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&soc {
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/* QUPv3 SE Instances
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* Qup0 0: SE 0
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* Qup0 1: SE 1
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* Qup0 2: SE 2
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* Qup0 3: SE 3
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* Qup0 4: SE 4
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* Qup0 5: SE 5
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* Qup0 6: SE 6
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* Qup0 7: SE 7
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*/
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x4ac0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
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<MASTER_QUP_0 SLAVE_EBI_CH0>;
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qcom,vote-for-bw;
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iommus = <&apps_smmu 0xe3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok"
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}
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@4a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x4a00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xf6 0x0>;
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qcom,max-num-gpii = <12>;
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interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0xf>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok"
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};
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/* Debug UART Instance */
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qupv3_se6_2uart: qcom,qup_uart@4a98000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x4a98000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_2uart_active>;
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pinctrl-1 = <&qupv3_se6_2uart_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se0_i2c: i2c@4a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se0_spi: spi@4a80000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@4a84000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a84000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_spi: spi@4a84000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a84000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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dmas = <&gpi_dma0 0 1 1 64 0>,
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<&gpi_dma0 1 1 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@4a88000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_spi: spi@4a88000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@4a8c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a8c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_spi: spi@4a8c000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a8c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_spi_active>;
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pinctrl-1 = <&qupv3_se3_spi_sleep>;
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dmas = <&gpi_dma0 0 3 1 64 0>,
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<&gpi_dma0 1 3 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@4a90000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a90000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_spi: spi@4a90000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a90000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_spi_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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dmas = <&gpi_dma0 0 4 1 64 0>,
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<&gpi_dma0 1 4 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@4a94000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a94000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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dmas = <&gpi_dma0 0 5 3 64 0>,
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<&gpi_dma0 1 5 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_spi: spi@4a94000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a94000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_spi_active>;
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pinctrl-1 = <&qupv3_se5_spi_sleep>;
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dmas = <&gpi_dma0 0 5 1 64 0>,
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<&gpi_dma0 1 5 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se6_i2c: i2c@4a98000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a98000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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dmas = <&gpi_dma0 0 6 3 64 0>,
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<&gpi_dma0 1 6 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se6_spi: spi@4a98000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a98000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_spi_active>;
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pinctrl-1 = <&qupv3_se6_spi_sleep>;
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dmas = <&gpi_dma0 0 6 1 64 0>,
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<&gpi_dma0 1 6 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se7_i2c_a: i2c@4a9c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a9c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_i2c_active_L0_a
|
|
&qupv3_se7_i2c_active_L1_a>;
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep_a>;
|
|
dmas = <&gpi_dma0 0 7 3 64 0>,
|
|
<&gpi_dma0 1 7 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_spi_a: spi@4a9c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x4a9c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_spi_active_L0_a
|
|
&qupv3_se7_spi_active_L1_a &qupv3_se7_spi_active_L2_a
|
|
&qupv3_se7_spi_active_L3_a>;
|
|
pinctrl-1 = <&qupv3_se7_spi_sleep_a>;
|
|
dmas = <&gpi_dma0 0 7 1 64 0>,
|
|
<&gpi_dma0 1 7 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <75000000>;
|
|
qcom,wrapper-core = <&qupv3_0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_i2c_b: i2c@4a9c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x4a9c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_i2c_active_L0_b
|
|
&qupv3_se7_i2c_active_L1_b>;
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep_b>;
|
|
dmas = <&gpi_dma0 0 7 3 64 0>,
|
|
<&gpi_dma0 1 7 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,wrapper-core = <&qupv3_0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_spi_b: spi@4a9c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x4a9c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_spi_active_L0_b
|
|
&qupv3_se7_spi_active_L1_b &qupv3_se7_spi_active_L2_b
|
|
&qupv3_se7_spi_active_L3_b>;
|
|
pinctrl-1 = <&qupv3_se7_spi_sleep_b>;
|
|
dmas = <&gpi_dma0 0 7 1 64 0>,
|
|
<&gpi_dma0 1 7 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <75000000>;
|
|
qcom,wrapper-core = <&qupv3_0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* HS UART Instance */
|
|
qupv3_se5_4uart: qcom,qup_uart@4a94000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0x4a94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&tlmm 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
pinctrl-names = "default", "active", "sleep";
|
|
pinctrl-0 = <&qupv3_se5_default_ctsrtsrx>,
|
|
<&qupv3_se5_default_tx>;
|
|
pinctrl-1 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
|
|
<&qupv3_se5_tx>;
|
|
pinctrl-2 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
|
|
<&qupv3_se5_tx>;
|
|
qcom,wakeup-byte = <0xFD>;
|
|
qcom,wrapper-core = <&qupv3_0>;
|
|
status = "disabled";
|
|
};
|
|
};
|