mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-09 12:24:07 -05:00
7c76276903
- Remove duplicate includes for gcc and regulator header files. - Move includes for common header files to quin-vm-common. - Add/Fix address and size cells values where missing/incorrect. - Add #interrupt-controller for vgic node. Change-Id: I488c79bfb5c54dee0c4cd219e8937794489051da
268 lines
6.9 KiB
Devicetree
268 lines
6.9 KiB
Devicetree
&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x1c00000 0x4000>,
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<0x1c06000 0x1000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>,
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<0x60200000 0x100000>,
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<0x60300000 0x3d00000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf", "io", "bars";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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qcom,phy-sequence = <0x0840 0x03 0x0
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0x0094 0x08 0x0
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0x0154 0x34 0x0
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0x016c 0x08 0x0
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0x0058 0x0f 0x0
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0x00a4 0x42 0x0
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0x0110 0x24 0x0
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0x011c 0x03 0x0
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0x0118 0xb4 0x0
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0x010c 0x02 0x0
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0x01bc 0x11 0x0
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0x00bc 0x82 0x0
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0x00d4 0x03 0x0
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0x00d0 0x55 0x0
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0x00cc 0x55 0x0
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0x00b0 0x1a 0x0
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0x00ac 0x0a 0x0
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0x00c4 0x68 0x0
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0x00e0 0x02 0x0
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0x00dc 0xaa 0x0
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0x00d8 0xab 0x0
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0x00b8 0x34 0x0
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0x00b4 0x14 0x0
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0x0158 0x01 0x0
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0x0074 0x06 0x0
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0x007c 0x16 0x0
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0x0084 0x36 0x0
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0x0078 0x06 0x0
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0x0080 0x16 0x0
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0x0088 0x36 0x0
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0x01b0 0x1e 0x0
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0x01ac 0xb9 0x0
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0x01b8 0x18 0x0
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0x01b4 0x94 0x0
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0x0050 0x07 0x0
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0x0010 0x00 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x029c 0x12 0x0
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0x0284 0x35 0x0
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0x023c 0x11 0x0
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0x051c 0x03 0x0
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0x0518 0x1c 0x0
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0x0524 0x1e 0x0
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0x04e8 0x00 0x0
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0x04ec 0x0e 0x0
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0x04f0 0x4a 0x0
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0x04f4 0x0f 0x0
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0x05b4 0x04 0x0
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0x0434 0x7f 0x0
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0x0444 0x70 0x0
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0x0510 0x17 0x0
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0x04d4 0x54 0x0
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0x04d8 0x07 0x0
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0x0598 0xd4 0x0
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0x059c 0x54 0x0
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0x05a0 0xdb 0x0
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0x05a4 0x3b 0x0
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0x05a8 0x31 0x0
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0x0584 0x24 0x0
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0x0588 0xe4 0x0
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0x058c 0xec 0x0
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0x0590 0x3b 0x0
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0x0594 0x36 0x0
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0x0570 0xff 0x0
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0x0574 0xff 0x0
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0x0578 0xff 0x0
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0x057c 0x7f 0x0
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0x0580 0x66 0x0
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0x04fc 0x00 0x0
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0x04f8 0xc0 0x0
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0x0460 0x30 0x0
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0x0464 0xc0 0x0
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0x05bc 0x0c 0x0
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0x04dc 0x0d 0x0
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0x0408 0x0c 0x0
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0x0414 0x03 0x0
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0x09a4 0x01 0x0
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0x0c90 0x00 0x0
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0x0c40 0x01 0x0
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0x0c48 0x01 0x0
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0x0c50 0x00 0x0
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0x0cbc 0x00 0x0
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0x0ce0 0x58 0x0
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0x0048 0x90 0x0
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0x0c1c 0xc1 0x0
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0x0988 0x88 0x0
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0x0998 0x0b 0x0
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0x08dc 0x0d 0x0
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0x09ec 0x01 0x0
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0x0800 0x00 0x0
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0x0844 0x03 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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perst-gpio = <&tlmm 35 0>;
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wake-gpio = <&tlmm 37 0>;
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gdsc-vdd-supply = <&pcie_0_gdsc>;
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vreg-1p8-supply = <&pm8150_2_l8>;
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vreg-0p9-supply = <&pm8150_2_l18>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_NOM 100000000>;
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qcom,no-l0s-supported;
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msi-parent = <&pcie0_msi>;
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qcom,ep-latency = <10>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,phy-status-offset = <0x814>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x840>;
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qcom,boot-option = <0x1>;
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linux,pci-domain = <0>;
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qcom,pcie-phy-ver = <2110>;
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qcom,use-19p2mhz-aux-clk;
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qcom,smmu-sid-base = <0x1d80>;
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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qcom,core-preset = <0x77777777>;
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iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
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<0x100 &apps_smmu 0x1d81 0x1>,
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<0x200 &apps_smmu 0x1d82 0x1>,
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<0x300 &apps_smmu 0x1d83 0x1>,
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<0x400 &apps_smmu 0x1d84 0x1>,
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<0x500 &apps_smmu 0x1d85 0x1>,
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<0x600 &apps_smmu 0x1d86 0x1>,
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<0x700 &apps_smmu 0x1d87 0x1>,
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<0x800 &apps_smmu 0x1d88 0x1>,
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<0x900 &apps_smmu 0x1d89 0x1>,
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<0xa00 &apps_smmu 0x1d8a 0x1>,
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<0xb00 &apps_smmu 0x1d8b 0x1>,
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<0xc00 &apps_smmu 0x1d8c 0x1>,
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<0xd00 &apps_smmu 0x1d8d 0x1>,
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<0xe00 &apps_smmu 0x1d8e 0x1>,
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<0xf00 &apps_smmu 0x1d8f 0x1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&dummycc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_PHY_AUX_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_phy_aux_clk";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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pcie_rc0: pcie_rc0 {
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#address-cells = <5>;
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#size-cells = <0>;
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reg = <0 0 0 0 0>;
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pci-ids = "17cb:0108";
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a00040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a00040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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};
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};
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