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The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin <[email protected]> Acked-by: Nicolas Ferre <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]> |
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| at91 | ||
| tegra | ||