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android_kernel_motorola_sm6375/qcom/sdxlemur.dtsi

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#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
#include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/sound/qcom,gpr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interconnect/qcom,sdxlemur.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Qualcomm Technologies, Inc. SDXLEMUR";
compatible = "qcom,sdxlemur";
qcom,msm-id = <458 0x10000>;
interrupt-parent = <&intc>;
aliases {
pci-domain0 = &pcie0; /* PCIe0 domain */
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
reserved_memory: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
cmd_db: reserved-memory@8fee0000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x8fee0000 0x20000>;
};
mpss_adsp_mem: mpss_adsp_region@90800000 {
no-map;
reg = <0x90800000 0x10000000>;
};
tz_mem: tz_mem_region@8ff00000 {
no-map;
reg = <0x8ff00000 0x600000>;
};
smem_mem: smem_region@8fe40000 {
no-map;
reg = <0x8fe40000 0xc0000>;
label = "smem_mem";
};
peripheral_mem: peripheral_region@8fd00000 {
no-map;
reg = <0x8fd00000 0x140000>;
};
/*
* The exact size of this region may vary based on DDR size.
* 0x100000 will be valid for all DDR sizes at the cost of
* slightly reducing the memory available for HLOS.
*/
peripheral_mem2: peripheral_region2@8fb00000 {
no-map;
reg = <0x8fb00000 0x100000>;
};
mpss_dsm: mpss_dsm_region@8c400000 {
no-map;
reg = <0x8c400000 0x3200000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x00000000 0xffffffff>;
reusable;
size = <0x400000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x00000000 0xffffffff>;
reusable;
alignment = <0x400000>;
size = <0xC00000>;
linux,cma-default;
};
audio_mem: audio_region@0 {
compatible = "shared-dma-pool";
no-map;
size = <0x400000>;
};
};
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&A7_SPC &A7_PC &CX_MIN>;
};
};
soc: soc { };
firmware: firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
intc: interrupt-controller@17800000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x17800000 0x1000>,
<0x17802000 0x1000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 12 0xf08>,
<1 10 0xf08>,
<1 11 0xf08>;
clock-frequency = <19200000>;
};
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17820000 0x1000>;
clock-frequency = <19200000>;
frame@17821000 {
frame-number = <0>;
interrupts = <0 7 0x4>,
<0 6 0x4>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
interrupts = <0 8 0x4>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
interrupts = <0 9 0x4>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
interrupts = <0 10 0x4>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
interrupts = <0 11 0x4>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
interrupts = <0 12 0x4>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
interrupts = <0 13 0x4>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
interrupts = <0 14 0x4>;
reg = <0x17829000 0x1000>;
status = "disabled";
};
};
restart_pshold: restart@c264000 {
compatible = "qcom,pshold";
reg = <0xc264000 0x4>,
<0x1fd3000 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1100000 0x2000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x800>;
};
watchdog: qcom,wdt@17817000 {
compatible = "qcom,msm-watchdog";
reg = <0x17817000 0x1000>;
reg-names = "wdt-base";
interrupts = <1 3 0>, <1 2 0>;
qcom,bark-time = <11000>;
qcom,pet-time = <10000>;
qcom,wakeup-enable;
};
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
rpmh {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xec>;
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic {
qcom,dump-size = <0x80000>;
qcom,dump-id = <0xe4>;
};
tmc_etf {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf1>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etf_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x102>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
};
qcom,msm-imem@1468f000 {
compatible = "qcom,msm-imem";
reg = <0x1468f000 0x1000>; /* Address and size of IMEM */
ranges = <0x0 0x1468f000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_pipe_clk: pcie-0-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_pipe_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
aopcc: clock-controller@0 {
compatible = "qcom,aop-qmp-clk";
mboxes = <&qmp_aop 0>;
mbox-names = "qdss_clk";
#clock-cells = <1>;
};
gcc: clock-controller@0x100000 {
compatible = "qcom,sdxlemur-gcc", "syscon";
reg = <0x100000 0x1f7400>;
reg-name = "cc_base";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_apsscc: syscon@17811000 {
compatible = "syscon";
reg = <0x17811000 0x20>;
};
clock_mccc: syscon@90b0000 {
compatible = "syscon";
reg = <0x90b0000 0x54>;
};
clock_debugcc: qcom,cc-debug {
compatible = "qcom,sdxlemur-debugcc";
qcom,gcc = <&gcc>;
qcom,apsscc = <&clock_apsscc>;
qcom,mccc = <&clock_mccc>;
clock-names = "xo_clk_src";
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
};
serial_uart: serial@831000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x831000 0x200>;
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_console_active>;
pinctrl-1 = <&uart3_console_sleep>;
status = "ok"
};
pil_modem: qcom,mss@4080000 {
compatible = "qcom,pil-tz-generic";
reg = <0x4080000 0x100>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mss-supply = <&VDD_MSS_LEVEL>;
qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
qcom,firmware-name = "modem";
memory-region = <&mpss_adsp_mem>;
qcom,pas-id = <4>;
qcom,smem-id = <421>;
qcom,sysmon-id = <0>;
qcom,ssctl-instance-id = <0x22>;
interrupts-extended = <&intc 0 250 1>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
status = "ok"
};
qnand_1: nand@1b00000 {
compatible = "qcom,msm-nand";
reg = <0x01b00000 0x1000>,
<0x01b04000 0x1c000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_QPIC_CLK>;
status = "disabled";
};
apsscc: clock-controller@17808100 {
compatible = "qcom,sdxlemur-apsscc";
clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>;
clock-names = "bi_tcxo_ao", "gpll0_out_even";
reg = <0x17810008 0x16>,
<0x17808100 0x100>;
reg-names = "apcs_cmd", "apcs_pll";
vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
qcom,speed0-bin-v0 =
< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
< 1497600000 RPMH_REGULATOR_LEVEL_TURBO>;
#reset-cells = <1>;
};
apps_rsc: rsc@17830000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x17830000 0x10000>,
<0x17840000 0x10000>;
reg-names = "drv-0", "drv-1";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <1>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 2>,
<WAKE_TCS 2>,
<CONTROL_TCS 1>;
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
system_pm {
compatible = "qcom,system-pm";
};
rpmhcc: clock-controller@1 {
compatible = "qcom,sdxlemur-rpmh-clk";
#clock-cells = <1>;
};
};
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdxlemur-pdc";
reg = <0xb210000 0x10000>;
qcom,pdc-ranges = <0 147 52>, <52 266 32>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
/* GCC GDSCs */
gcc_pcie_gdsc: qcom,gdsc@143004 {
compatible = "qcom,gdsc";
reg = <0x143004 0x4>;
regulator-name = "gcc_pcie_gdsc";
};
gcc_usb30_gdsc: qcom,gdsc@117004 {
compatible = "qcom,gdsc";
reg = <0x117004 0x4>;
regulator-name = "gcc_usb30_gdsc";
};
system_noc: interconnect@1620000 {
compatible = "qcom,sdxlemur-system_noc";
reg = <0x1620000 0x31200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mem_noc: interconnect@9680000 {
compatible = "qcom,sdxlemur-mem_noc";
reg = <0x9680000 0x27200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect {
compatible = "qcom,sdxlemur-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
cache-controller@9200000 {
compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
reg = <0x9200000 0x50000>;
reg-names = "llcc_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&aopcc QDSS_CLK>;
clock-names = "aopcc_closks";
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
apcs_glb: mailbox@0x17811000 {
compatible = "qcom,sdxlemur-apcs-gcc";
reg = <0x17811000 0xb9>;
#mbox-cells = <1>;
};
qcom,smp2p-modem@1799000c {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&apcs_glb 15>;
mbox-names = "mpss_smem";
interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "modem_apps";
qcom,intents = <0x200 20>;
reg = <GPR_DOMAIN_MODEM>;
spf_core {
compatible = "qcom,spf_core";
reg = <GPR_SVC_ADSP_CORE>;
};
audio-pkt {
compatible = "qcom,audio-pkt";
qcom,audiopkt-ch-name = "apr_audio_svc";
reg = <GPR_SVC_MAX>;
};
audio_prm {
compatible = "qcom,audio_prm";
reg = <GPR_SVC_ASM>;
};
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-data5-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA5_CNTL";
qcom,glinkpkt-dev-name = "smdcntl0";
};
qcom,glinkpkt-data6-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA6_CNTL";
qcom,glinkpkt-dev-name = "smdcntl1";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
qcom,glinkpkt-data21 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA21";
qcom,glinkpkt-dev-name = "smd21";
};
qcom,glinkpkt-data22 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA22";
qcom,glinkpkt-dev-name = "smd22";
};
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
reg = <0xc310000 0x1000>;
reg-names = "msgram";
mboxes = <&apcs_glb 0>;
interrupts = <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>;
label = "aop";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
aop-msg-client {
compatible = "qcom,debugfs-qmp-client";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
};
qcom,ipa_fws {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "ipa_fws";
qcom,pil-force-shutdown;
};
ipa_hw: qcom,ipa@03e00000 {
compatible = "qcom,ipa";
mboxes = <&qmp_aop 0>;
reg =
<0x3e00000 0x84000>,
<0x3e04000 0xfc000>;
reg-names = "ipa-base", "gsi-base";
qcom,ipa-cfg-offset = <0x0140000>;
interrupts =
<0 241 IRQ_TYPE_LEVEL_HIGH>,
<0 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
qcom,ipa-hw-ver = <21>; /* IPA core version = IPAv5.0 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <0>; /* MDM platform */
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
qcom,modem-cfg-emb-pipe-flt;
qcom,use-xbl-boot;
qcom,arm-smmu;
qcom,smmu-fast-map;
qcom,ipa-wdi3-over-gsi;
qcom,lan-rx-napi;
qcom,wan-use-skb-page;
qcom,tx-wrapper-cache-max-size = <400>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_IPA_CLK>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <4>;
interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&system_noc MASTER_IPA &system_noc SLAVE_IMEM>,
<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<150000 600000 150000 1804000 75000 300000 0 76800>;
/* SVS */
qcom,svs =
<625000 1200000 625000 3072000 312500 700000 0 150000>;
/* NOMINAL */
qcom,nominal =
<1250000 2400000 1250000 6220800 625000 1500000 0 400000>;
/* TURBO */
qcom,turbo =
<2000000 3500000 2000000 7219200 1000000 1920000 0 400000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
"TURBO";
qcom,throughput-threshold = <600 2500 5000>;
qcom,scaling-exceptions = <>;
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x5E0 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,additional-mapping =
/* modem tables in IMEM */
<0x14688000 0x14688000 0x3000>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,ipa-q6-smem-size = <36864>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x5E1 0x0>;
dma-coherent;
qcom,iommu-dma = "atomic";
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x5E2 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,iommu-dma = "atomic";
};
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x5E3 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <>;
};
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
thermal_zones: thermal-zones {
};
};
#include "sdxlemur-pinctrl.dtsi"
#include "sdxlemur-stub-regulator.dtsi"
#include "msm-arm-smmu-sdxlemur.dtsi"
#include "sdxlemur-ion.dtsi"
#include "sdxlemur-usb.dtsi"
#include "sdxlemur-pm.dtsi"
#include "sdxlemur-pcie.dtsi"
#include "sdxlemur-blsp.dtsi"
#include "sdxlemur-audio.dtsi"
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