mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
3f9968c71f
GPUCC clock nodes is required for clocks client to request, so add support for the same. Also add the GDSCs required by clients for MONACO. Change-Id: I2eb3f35e48a1f7f44c93df64384cee1af871416a
91 lines
2.1 KiB
Devicetree
91 lines
2.1 KiB
Devicetree
&soc {
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/* GDSCs in GCC */
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gcc_camss_top_gdsc: qcom,gdsc@1458004 {
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compatible = "qcom,gdsc";
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reg = <0x1458004 0x4>;
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regulator-name = "gcc_camss_top_gdsc";
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status = "disabled";
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};
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gcc_usb20_prim_gdsc: qcom,gdsc@141c004 {
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compatible = "qcom,gdsc";
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reg = <0x141c004 0x4>;
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regulator-name = "gcc_usb20_prim_gdsc";
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status = "disabled";
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};
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gcc_vcodec0_gdsc: qcom,gdsc@14580ac {
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compatible = "qcom,gdsc";
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reg = <0x14580ac 0x4>;
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regulator-name = "gcc_vcodec0_gdsc";
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status = "disabled";
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};
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gcc_venus_gdsc: qcom,gdsc@1458088 {
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compatible = "qcom,gdsc";
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reg = <0x1458088 0x4>;
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regulator-name = "gcc_venus_gdsc";
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
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compatible = "qcom,gdsc";
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reg = <0x147d078 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
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compatible = "qcom,gdsc";
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reg = <0x147d074 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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/* GDSCs in DISPCC */
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mdss_core_gdsc: qcom,gdsc@5f03000 {
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compatible = "qcom,gdsc";
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reg = <0x5f03000 0x4>;
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regulator-name = "mdss_core_gdsc";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GDSCs in GPUCC */
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gpu_gx_sw_reset: syscon@5994008 {
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compatible = "syscon";
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reg = <0x5994008 0x4>;
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};
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gpu_cx_hw_ctrl: syscon@5994540 {
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compatible = "syscon";
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reg = <0x5994540 0x4>;
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};
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gpu_gx_domain_addr: syscon@5994508 {
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compatible = "syscon";
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reg = <0x5994508 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@5994064 {
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compatible = "qcom,gdsc";
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reg = <0x5994064 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@599400c {
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compatible = "qcom,gdsc";
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reg = <0x599400c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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sw-reset = <&gpu_gx_sw_reset>;
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domain-addr = <&gpu_gx_domain_addr>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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};
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