mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
7c138aad2c
Enable Change detect for sdhci for 6155/8155/8195 linux guest. Change-Id: Ia5fbad43ddaf3d8ff13cb2fabfbbfce5a9d6f3bb
611 lines
14 KiB
Devicetree
611 lines
14 KiB
Devicetree
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/clock/qcom,scc-sm6150.h>
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#include "quin-vm-common.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine";
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qcom,msm-name = "SA6155P";
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qcom,msm-id = <377 0x0>;
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aliases {
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hsuart0 = &qupv3_se7_4uart;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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capacity-dmips-mhz = <1024>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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capacity-dmips-mhz = <1024>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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capacity-dmips-mhz = <347>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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capacity-dmips-mhz = <347>;
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};
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CPU4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x4>;
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capacity-dmips-mhz = <347>;
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};
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CPU5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x5>;
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capacity-dmips-mhz = <347>;
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};
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CPU6: cpu@6 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x6>;
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capacity-dmips-mhz = <347>;
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};
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CPU7: cpu@7 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x7>;
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capacity-dmips-mhz = <347>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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core2 {
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cpu = <&CPU4>;
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};
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core3 {
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cpu = <&CPU5>;
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};
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core4 {
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cpu = <&CPU6>;
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};
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core5 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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aliases {
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sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
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};
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};
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&soc {
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VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL:
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pm6155_1_s2_level: regulator-pm6155-1-s2-level {
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compatible = "qcom,stub-regulator";
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regulator-name = "pm6155_1_s2_level";
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regulator-min-microvolt
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= <RPMH_REGULATOR_LEVEL_RETENTION>;
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regulator-max-microvolt
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= <RPMH_REGULATOR_LEVEL_MAX>;
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};
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/* PWR_CTR1_VDD_1P8 supply */
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vreg_conn_1p8: vreg_conn_1p8 {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_1p8";
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&pm6155_1_gpios 1 0>;
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};
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/* PWR_CTR2_VDD_PA supply */
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vreg_conn_pa: vreg_conn_pa {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_pa";
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&pm6155_1_gpios 6 0>;
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};
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vreg_wlan: vreg_wlan {
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compatible = "qcom,stub-regulator";
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regulator-name = "vreg_wlan";
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};
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cnss_pcie: qcom,cnss-qca-converged {
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compatible = "qcom,cnss-qca-converged";
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qcom,converged-dt;
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qcom,wlan-rc-num = <0>;
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qcom,bus-type=<0>;
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qcom,notify-modem-status;
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qcom,msm-bus,name = "msm-cnss";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<45 512 0 0>, <1 512 0 0>,
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/* Upto 200 Mbps */
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<45 512 41421 655360>, <1 512 41421 655360>,
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/* Upto 400 Mbps */
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<45 512 98572 655360>, <1 512 98572 1600000>,
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/* Upto 800 Mbps */
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<45 512 207108 1146880>, <1 512 207108 3124992>;
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#address-cells=<1>;
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#size-cells=<1>;
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ranges = <0x10000000 0x10000000 0x10000000>,
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<0x20000000 0x20000000 0x10000>,
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<0xa0000000 0xa0000000 0x10000000>,
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<0xb0000000 0xb0000000 0x10000>;
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vdd-wlan-ctrl1-supply = <&vreg_conn_pa>;
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vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>;
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vdd-wlan-supply = <&vreg_wlan>;
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vdd-wlan-rfa1-supply = <&pm6155_1_s6>;
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vdd-wlan-rfa2-supply = <&pm6155_1_s5>;
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vdd-wlan-rfa3-supply = <&pm6155_1_l15>;
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wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2";
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qcom,vdd-wlan-ctrl1-info = <0 0 0 0>;
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qcom,vdd-wlan-ctrl2-info = <0 0 0 0>;
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wlan-en-gpio = <&tlmm 98 0>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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chip_cfg@0 {
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reg = <0x10000000 0x10000000>,
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<0x20000000 0x10000>;
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reg-names = "smmu_iova_base", "smmu_iova_ipa";
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supported-ids = <0x003e>;
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wlan_vregs = "vdd-wlan";
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qcom,vdd-wlan-info = <0 0 0 10>;
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qcom,smmu-s1-enable;
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qcom,wlan-ramdump-dynamic = <0x200000>;
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};
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chip_cfg@1 {
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reg = <0xa0000000 0x10000000>,
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<0xb0000000 0x10000>;
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reg-names = "smmu_iova_base", "smmu_iova_ipa";
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supported-ids = <0x1101>;
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wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2",
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"vdd-wlan-rfa3";
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qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>;
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qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>;
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qcom,vdd-wlan-rfa3-info = <1904000 1904000 0 0>;
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qcom,wlan-ramdump-dynamic = <0x400000>;
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mhi,max-channels = <30>;
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mhi,timeout = <10000>;
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mhi_channels {
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mhi_chan@0 {
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reg = <0>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@1 {
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reg = <1>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@4 {
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reg = <4>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@5 {
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reg = <5>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@20 {
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reg = <20>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <1>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-start;
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};
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mhi_chan@21 {
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reg = <21>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-queue;
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mhi,auto-start;
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};
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};
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mhi_events {
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mhi_event@0 {
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mhi,num-elements = <32>;
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mhi,intmod = <1>;
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mhi,msi = <1>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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mhi,data-type = <1>;
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};
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mhi_event@1 {
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mhi,num-elements = <256>;
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mhi,intmod = <1>;
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mhi,msi = <2>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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};
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};
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};
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};
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apps_smmu: apps-smmu@0x15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x80000>,
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<0x150c2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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qcom_seecom: qseecom@86d00000 {
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compatible = "qcom,qseecom";
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reg = <0x86d00000 0xe00000>;
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reg-names = "secapp-region";
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memory-region = <&qseecom_mem>;
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qcom,hlos-num-ce-hw-instances = <1>;
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qcom,hlos-ce-hw-instance = <0>;
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qcom,qsee-ce-hw-instance = <0>;
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qcom,disk-encrypt-pipe-pair = <2>;
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qcom,no-clock-support;
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qcom,qsee-reentrancy-support = <2>;
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};
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qcom_rng: qrng@793000 {
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compatible = "qcom,msm-rng";
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reg = <0x793000 0x1000>;
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qcom,no-qrng-config;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "km_clk_src";
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm6150-pdc";
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reg = <0xb220000 0x30000>;
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qcom,pdc-ranges = <6 486 1>, <8 488 4>, <94 609 1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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sdhc_2: sdhci@8804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x8804000 0x1000>;
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reg-names = "hc_mem";
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_AHB_CLK>,
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<&gcc GCC_SDCC2_APPS_CLK>;
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clock-names = "iface", "core";
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bus-width = <4>;
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qcom,restore-after-cx-collapse;
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qcom,msm-bus,name = "sdhc2";
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qcom,msm-bus,num-cases = <6>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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/* No vote */
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<0 0>, <0 0>,
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/* 25 MB/s */
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<65360 100000>, <100000 100000>,
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/* 50 MB/s */
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<130718 200000>, <133320 133320>,
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/* 100 MB/s */
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<261438 200000>, <150000 150000>,
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/* 200 MB/s */
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<261438 400000>, <300000 300000>,
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/* Max. bandwidth */
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<1338562 4096000>, <1338562 4096000>;
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/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
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qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
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qcom,devfreq,freq-table = <50000000 201500000>;
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vdd-supply = <&pm6155_1_l10>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 800000>;
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|
vdd-io-supply = <&pm6155_1_l2>;
|
|
qcom,vdd-io-voltage-level = <1800000 3100000>;
|
|
qcom,vdd-io-current-level = <0 22000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&sdc2_on>;
|
|
pinctrl-1 = <&sdc2_off>;
|
|
|
|
cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x3f>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0xc0>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
msm_gpu_hyp: qcom,hgsl {
|
|
compatible = "qcom,hgsl";
|
|
|
|
/* 6155 have no Doorbell, only keep ifence */
|
|
db-off = <1>;
|
|
};
|
|
|
|
bluetooth: bt-qca-auto-converged {
|
|
compatible = "qcom,qca-auto-converged";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&bt_en_active>;
|
|
/* BT_EN */
|
|
qcom,bt-reset-gpio = <&tlmm 85 0>;
|
|
/* PWR_CTR1_VDD_PA */
|
|
qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>;
|
|
/* PWR_CTR2_VDD_1P8 */
|
|
qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>;
|
|
qcom,bt-vdd-rfa1-supply = <&pm6155_1_s6>;
|
|
qcom,bt-vdd-rfa2-supply = <&pm6155_1_s5>;
|
|
qcom,bt-vdd-rfa3-supply = <&pm6155_1_l15>;
|
|
|
|
/* <vol_min, vol_max, load_curr, is_retention_supp> */
|
|
qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>;
|
|
qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>;
|
|
qcom,bt-vdd-rfa3-config = <1904000 1904000 0 0>;
|
|
};
|
|
};
|
|
|
|
®ulator {
|
|
usb30_prim_gdsc: usb30_prim_gdsc {
|
|
regulator-name = "usb30_prim_gdsc";
|
|
};
|
|
|
|
usb20_sec_gdsc: usb20_sec_gdsc {
|
|
regulator-name = "usb20_sec_gdsc";
|
|
};
|
|
|
|
pcie_0_gdsc: pcie_0_gdsc {
|
|
regulator-name = "pcie_0_gdsc";
|
|
};
|
|
|
|
L2A: pm6155_1_l2: regulator-pm6155-1-l2 {
|
|
regulator-name = "ldoa2";
|
|
regulator-min-microvolt = <1650000>;
|
|
regulator-max-microvolt = <3100000>;
|
|
};
|
|
|
|
L5A: pm6155_1_l5: regulator-pm6155-1-l5 {
|
|
regulator-name = "ldoa5";
|
|
regulator-min-microvolt = <875000>;
|
|
regulator-max-microvolt = <975000>;
|
|
};
|
|
|
|
L10A: pm6155_1_l10: regulator-pm6155-1-l10 {
|
|
regulator-name = "ldoa10";
|
|
regulator-min-microvolt = <2950000>;
|
|
regulator-max-microvolt = <3312000>;
|
|
};
|
|
|
|
L12A: pm6155_1_l12: regulator-pm6155-1-l12 {
|
|
regulator-name = "ldoa12";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1890000>;
|
|
};
|
|
|
|
L13A: pm6155_1_l13: regulator-pm6155-1-l13 {
|
|
regulator-name = "ldoa13";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3230000>;
|
|
};
|
|
|
|
S6A: pm6155_1_s6: regulator-pm6155-1-s6 {
|
|
regulator-name = "smpa6";
|
|
regulator-min-microvolt = <947000>;
|
|
regulator-max-microvolt = <1404000>;
|
|
};
|
|
|
|
S5A: pm6155_1_s5: regulator-pm6155-1-s5 {
|
|
regulator-name = "smpa5";
|
|
regulator-min-microvolt = <1896000>;
|
|
regulator-max-microvolt = <2040000>;
|
|
};
|
|
|
|
L15A: pm6155_1_l15: regulator-pm6155-1-l15 {
|
|
regulator-name = "ldoa15";
|
|
regulator-min-microvolt = <1904000>;
|
|
regulator-max-microvolt = <1904000>;
|
|
};
|
|
};
|
|
|
|
&firmware {
|
|
scm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
};
|
|
|
|
#include "sm6150-pinctrl.dtsi"
|
|
#include "sa6155p-vm-usb.dtsi"
|
|
#include "sa6155p-vm-pcie.dtsi"
|
|
#include "sm6150-qupv3.dtsi"
|
|
#include "sa8155-vm-audio.dtsi"
|
|
#include "pm6155-vm.dtsi"
|
|
#include "sa6155p-vm-cnss.dtsi"
|
|
|
|
&tlmm {
|
|
qcom,gpio-irq-map = <99 94>;
|
|
};
|
|
|
|
&qupv3_0 {
|
|
/delete-property/ qcom,msm-bus,num-paths;
|
|
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
|
qcom,iommu-dma = "bypass";
|
|
};
|
|
|
|
&qupv3_1 {
|
|
/delete-property/ qcom,msm-bus,num-paths;
|
|
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
|
qcom,iommu-dma = "bypass";
|
|
};
|
|
|