mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
7c138aad2c
Enable Change detect for sdhci for 6155/8155/8195 linux guest. Change-Id: Ia5fbad43ddaf3d8ff13cb2fabfbbfce5a9d6f3bb
896 lines
21 KiB
Devicetree
896 lines
21 KiB
Devicetree
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include "quin-vm-common.dtsi"
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#include "pm8150-vm.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine";
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qcom,msm-name = "SA8155 V2";
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qcom,msm-id = <362 0x20000>;
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aliases {
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hsuart0 = &qupv3_se13_4uart;
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sdhc2 = &sdhc_2; /* SDC2 SD card slot */
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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capacity-dmips-mhz = <1024>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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capacity-dmips-mhz = <902>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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capacity-dmips-mhz = <902>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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capacity-dmips-mhz = <902>;
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};
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CPU4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x4>;
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capacity-dmips-mhz = <320>;
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};
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CPU5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x5>;
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capacity-dmips-mhz = <320>;
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};
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CPU6: cpu@6 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x6>;
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capacity-dmips-mhz = <320>;
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};
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CPU7: cpu@7 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x7>;
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capacity-dmips-mhz = <320>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU1>;
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};
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core1 {
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cpu = <&CPU2>;
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};
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core2 {
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cpu = <&CPU3>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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};
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&soc {
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/* Rome 3.3V supply */
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vreg_wlan: vreg_wlan {
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compatible = "qcom,stub-regulator";
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regulator-name = "vreg_wlan";
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};
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/* PWR_CTR2_VDD_1P8 supply */
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vreg_conn_1p8: vreg_conn_1p8 {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_1p8";
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pinctrl-names = "default";
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pinctrl-0 = <&conn_power_1p8_active>;
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&tlmm 173 0>;
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};
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/* PWR_CTR1_VDD_PA supply */
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vreg_conn_pa: vreg_conn_pa {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_pa";
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pinctrl-names = "default";
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pinctrl-0 = <&conn_power_pa_active>;
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&tlmm 174 0>;
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};
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VDD_CX_LEVEL: VDD_MMCX_LEVEL:
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S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level {
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compatible = "qcom,stub-regulator";
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regulator-name = "pm8150_2_s9_level";
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regulator-min-microvolt
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= <RPMH_REGULATOR_LEVEL_RETENTION>;
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regulator-max-microvolt
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= <RPMH_REGULATOR_LEVEL_MAX>;
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};
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qcom,cnss-qca-converged {
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compatible = "qcom,cnss-qca-converged";
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qcom,converged-dt;
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qcom,wlan-rc-num = <0>;
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qcom,bus-type=<0>;
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qcom,notify-modem-status;
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qcom,msm-bus,name = "msm-cnss";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<45 512 0 0>, <1 512 0 0>,
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/* Upto 200 Mbps */
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<45 512 41421 655360>, <1 512 41421 655360>,
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/* Upto 400 Mbps */
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<45 512 98572 655360>, <1 512 98572 1600000>,
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/* Upto 800 Mbps */
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<45 512 207108 1146880>, <1 512 207108 3124992>;
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#address-cells=<1>;
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#size-cells=<1>;
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ranges = <0xb0000000 0xb0000000 0x10000>;
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vdd-wlan-ctrl1-supply = <&vreg_conn_pa>;
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vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>;
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vdd-wlan-supply = <&vreg_wlan>;
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vdd-wlan-aon-supply = <&pm8150_1_s6>;
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vdd-wlan-rfa1-supply = <&pm8150_2_s4>;
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vdd-wlan-rfa2-supply = <&pm8150_2_s5>;
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vdd-wlan-rfa3-supply = <&pm8150_2_l15>;
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wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2";
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qcom,vdd-wlan-ctrl1-config = <0 0 0 0>;
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qcom,vdd-wlan-ctrl2-config = <0 0 0 0>;
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wlan-en-gpio = <&tlmm 169 0>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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chip_cfg@0 {
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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supported-ids = <0x003e>;
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wlan_vregs = "vdd-wlan";
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qcom,vdd-wlan-info = <0 0 0 10>;
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qcom,smmu-s1-enable;
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qcom,wlan-ramdump-dynamic = <0x200000>;
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};
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chip_cfg@1 {
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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supported-ids = <0x1101>;
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wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",
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"vdd-wlan-rfa2", "vdd-wlan-rfa3";
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qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>;
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qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>;
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qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>;
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qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>;
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qcom,wlan-ramdump-dynamic = <0x400000>;
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mhi,max-channels = <30>;
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mhi,timeout = <10000>;
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mhi,buffer-len = <0x8000>;
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mhi_channels {
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#address-cells = <1>;
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#size-cells = <0>;
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mhi_chan@0 {
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reg = <0>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@1 {
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reg = <1>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@4 {
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reg = <4>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@5 {
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reg = <5>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@20 {
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reg = <20>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <1>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-start;
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};
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mhi_chan@21 {
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reg = <21>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-queue;
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mhi,auto-start;
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};
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};
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mhi_events {
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mhi_event@0 {
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mhi,num-elements = <32>;
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mhi,intmod = <1>;
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mhi,msi = <1>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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mhi,data-type = <1>;
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};
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mhi_event@1 {
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mhi,num-elements = <256>;
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mhi,intmod = <1>;
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mhi,msi = <2>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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};
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};
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};
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chip_cfg@2 {
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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supported-ids = <0x1102>;
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wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",
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"vdd-wlan-rfa2", "vdd-wlan-rfa3";
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qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>;
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qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>;
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qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>;
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qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>;
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qcom,wlan-ramdump-dynamic = <0x300000>;
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mhi,max-channels = <30>;
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mhi,timeout = <10000>;
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mhi,ee = <0x3>, <0x4>;
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mhi,ee-names = "SBL", "RDDM";
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mhi,bhie-offset = <0x0324>;
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mhi_channels {
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#address-cells = <1>;
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#size-cells = <0>;
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mhi_chan@0 {
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reg = <0>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@1 {
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reg = <1>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@4 {
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reg = <4>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@5 {
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reg = <5>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@16 {
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reg = <16>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <1>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-start;
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};
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mhi_chan@17 {
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reg = <17>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-queue;
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mhi,auto-start;
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};
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};
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mhi_events {
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mhi_event@0 {
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mhi,num-elements = <32>;
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mhi,intmod = <1>;
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mhi,msi = <1>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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mhi,data-type = <1>;
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};
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mhi_event@1 {
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mhi,num-elements = <256>;
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mhi,intmod = <1>;
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mhi,msi = <2>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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};
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};
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};
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};
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apps_smmu: apps-smmu@0x15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x100000>,
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<0x15182000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ptp_virtual {
|
|
compatible = "qcom,ptp_virtual";
|
|
reg = <0xeb600000 0x1000>;
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc_mem";
|
|
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
bus-width = <4>;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
qcom,msm-bus,name = "sdhc2";
|
|
qcom,msm-bus,num-cases = <6>;
|
|
qcom,msm-bus,num-paths = <2>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
/* No vote */
|
|
<0 0>, <0 0>,
|
|
/* 25 MB/s */
|
|
<65360 100000>, <100000 100000>,
|
|
/* 50 MB/s */
|
|
<130718 200000>, <133320 133320>,
|
|
/* 100 MB/s */
|
|
<261438 200000>, <150000 150000>,
|
|
/* 200 MB/s */
|
|
<261438 400000>, <300000 300000>,
|
|
/* Max. bandwidth */
|
|
<1338562 4096000>, <1338562 4096000>;
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
|
|
|
|
qcom,devfreq,freq-table = <50000000 201500000>;
|
|
|
|
vdd-supply = <&pm8150_1_l17>;
|
|
qcom,vdd-voltage-level = <2950000 2960000>;
|
|
qcom,vdd-current-level = <200 800000>;
|
|
|
|
vdd-io-supply = <&pm8150_2_l13>;
|
|
qcom,vdd-io-voltage-level = <1808000 2960000>;
|
|
qcom,vdd-io-current-level = <200 22000>;
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&sdc2_on>;
|
|
pinctrl-1 = <&sdc2_off>;
|
|
|
|
cd-gpios = <&pm8150_gpios 4 GPIO_ACTIVE_LOW>;
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x3f>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0xc0>;
|
|
vote = <44>;
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sm8150-pdc";
|
|
reg = <0xb220000 0x30000>;
|
|
qcom,pdc-ranges = <6 486 6>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tcsr_compute_signal_glb: syscon@0x1fd8000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fd8000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_sender0: syscon@0x1fd9000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fd9000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_sender1: syscon@0x1fdd000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fdd000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fdb000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fdf000 0x1000>;
|
|
};
|
|
|
|
hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
|
|
compatible = "qcom,hgsl-tcsr-sender";
|
|
syscon = <&tcsr_compute_signal_sender0>;
|
|
syscon-glb = <&tcsr_compute_signal_glb>;
|
|
};
|
|
|
|
hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
|
|
compatible = "qcom,hgsl-tcsr-sender";
|
|
syscon = <&tcsr_compute_signal_sender1>;
|
|
syscon-glb = <&tcsr_compute_signal_glb>;
|
|
};
|
|
|
|
hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
|
|
compatible = "qcom,hgsl-tcsr-receiver";
|
|
syscon = <&tcsr_compute_signal_receiver0>;
|
|
interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
|
|
compatible = "qcom,hgsl-tcsr-receiver";
|
|
syscon = <&tcsr_compute_signal_receiver1>;
|
|
interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
msm_gpu_hyp: qcom,hgsl@0x2c00000 {
|
|
compatible = "qcom,hgsl";
|
|
reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
|
|
reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
|
|
|
|
qcom,glb-db-senders = <&hgsl_tcsr_sender0
|
|
&hgsl_tcsr_sender1>;
|
|
qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
|
|
&hgsl_tcsr_receiver1>;
|
|
};
|
|
|
|
qtee_shmbridge {
|
|
compatible = "qcom,tee-shared-memory-bridge";
|
|
};
|
|
|
|
qcom_qseecom: qseecom@87900000 {
|
|
compatible = "qcom,qseecom";
|
|
reg = <0x87900000 0x2200000>;
|
|
reg-names = "secapp-region";
|
|
memory-region = <&qseecom_mem>;
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
|
qcom,no-clock-support;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
};
|
|
|
|
subsys_notif_virt: qcom,subsys_notif_virt@2D000000 {
|
|
compatible = "qcom,subsys-notif-virt";
|
|
reg = <0x2D000000 0x400>;
|
|
reg-names = "vdev_base";
|
|
adsp {
|
|
subsys-name = "adsp";
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "state-irq";
|
|
type = "virtual";
|
|
offset = <0>;
|
|
};
|
|
|
|
wlan {
|
|
subsys-name = "wlan";
|
|
type = "native";
|
|
offset = <512>;
|
|
};
|
|
};
|
|
|
|
bluetooth: bt-qca-auto-converged {
|
|
compatible = "qcom,qca-auto-converged";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&bt_en_active>;
|
|
/* BT_EN */
|
|
qcom,bt-reset-gpio = <&tlmm 172 0>;
|
|
/* PWR_CTR1_VDD_PA */
|
|
qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>;
|
|
/* PWR_CTR2_VDD_1P8 */
|
|
qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>;
|
|
qcom,bt-vdd-aon-supply = <&pm8150_1_s6>;
|
|
qcom,bt-vdd-rfa1-supply = <&pm8150_2_s4>;
|
|
qcom,bt-vdd-rfa2-supply = <&pm8150_2_s5>;
|
|
qcom,bt-vdd-rfa3-supply = <&pm8150_2_l15>;
|
|
|
|
/* <vol_min, vol_max, load_curr, is_retention_supp> */
|
|
qcom,bt-vdd-aon-config = <1055000 1055000 0 0>;
|
|
qcom,bt-vdd-rfa1-config = <1370000 1370000 0 0>;
|
|
qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>;
|
|
qcom,bt-vdd-rfa3-config = <1900000 1900000 450000 0>;
|
|
};
|
|
|
|
qcom_rng: qrng@793000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x793000 0x1000>;
|
|
qcom,no-qrng-config;
|
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
|
clock-names = "km_clk_src";
|
|
};
|
|
};
|
|
|
|
®ulator {
|
|
usb30_prim_gdsc: usb30_prim_gdsc {
|
|
regulator-name = "usb30_prim_gdsc";
|
|
};
|
|
|
|
usb30_sec_gdsc: usb30_sec_gdsc {
|
|
regulator-name = "usb30_sec_gdsc";
|
|
};
|
|
|
|
pcie_0_gdsc: pcie_0_gdsc {
|
|
regulator-name = "pcie_0_gdsc";
|
|
};
|
|
|
|
pcie_1_gdsc: pcie_1_gdsc {
|
|
regulator-name = "pcie_1_gdsc";
|
|
};
|
|
|
|
L2A: pm8150_1_l2: regulator-pm8150-1-l2 {
|
|
regulator-name = "ldoa2";
|
|
regulator-min-microvolt = <3072000>;
|
|
regulator-max-microvolt = <3072000>;
|
|
};
|
|
|
|
L5A: pm8150_1_l5: regulator-pm8150-1-l5 {
|
|
regulator-name = "ldoa5";
|
|
regulator-min-microvolt = <880000>;
|
|
regulator-max-microvolt = <880000>;
|
|
};
|
|
|
|
L12A: pm8150_1_l12: regulator-pm8150-1-l12 {
|
|
regulator-name = "ldoa12";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
L17A: pm8150_1_l17: regulator-pm8150-1-l17 {
|
|
regulator-name = "ldoa17";
|
|
regulator-min-microvolt = <2704000>;
|
|
regulator-max-microvolt = <2960000>;
|
|
};
|
|
|
|
L8C: pm8150_2_l8: regulator-pm8150-2-l8 {
|
|
regulator-name = "ldoc8";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-allow-set-load;
|
|
};
|
|
|
|
L13C: pm8150_2_l13: regulator-pm8150-2-l13 {
|
|
regulator-name = "ldoc13";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <2960000>;
|
|
};
|
|
|
|
L15C: pm8150_2_l15: regulator-pm8150-2-l15 {
|
|
regulator-name = "ldoc15";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1904000>;
|
|
};
|
|
|
|
L18C: pm8150_2_l18: regulator-pm8150-2-l18 {
|
|
regulator-name = "ldoc18";
|
|
regulator-min-microvolt = <880000>;
|
|
regulator-max-microvolt = <880000>;
|
|
regulator-allow-set-load;
|
|
};
|
|
|
|
S6A: pm8150_1_s6: regulator-pm8150-1-s6 {
|
|
regulator-name = "smpa6";
|
|
regulator-min-microvolt = <600000>;
|
|
regulator-max-microvolt = <1352000>;
|
|
};
|
|
|
|
S4C: pm8150_2_s4: regulator-pm8150-2-s4 {
|
|
regulator-name = "smpc4";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
};
|
|
|
|
S5C: pm8150_2_s5: regulator-pm8150-2-s5 {
|
|
regulator-name = "smpc5";
|
|
regulator-min-microvolt = <1824000>;
|
|
regulator-max-microvolt = <2040000>;
|
|
};
|
|
};
|
|
|
|
&firmware {
|
|
scm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
};
|
|
|
|
#include "sm8150-pinctrl.dtsi"
|
|
#include "sm8150-slpi-pinctrl.dtsi"
|
|
#include "sa8155-vm-usb.dtsi"
|
|
#include "sa8155-vm-pcie.dtsi"
|
|
#include "sm8150-qupv3.dtsi"
|
|
#include "sm8150-ssc-qupv3.dtsi"
|
|
#include "sa8155-vm-audio.dtsi"
|
|
|
|
&tlmm {
|
|
/delete-property/ wakeup-parent;
|
|
};
|
|
|
|
&slpi_tlmm {
|
|
status = "ok"
|
|
};
|
|
|
|
&pcie_rc0 {
|
|
cnss_pci: cnss_pci {
|
|
reg = <0 0 0 0 0>;
|
|
qcom,iommu-group = <&cnss_pci_iommu_group>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cnss_pci_iommu_group: cnss_pci_iommu_group {
|
|
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-faults = "stall-disable", "no-CFRE",
|
|
"non-fatal";
|
|
};
|
|
};
|
|
};
|
|
|
|
&qupv3_0 {
|
|
/delete-property/ qcom,msm-bus,num-paths;
|
|
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
|
qcom,iommu-dma = "bypass";
|
|
};
|
|
|
|
&qupv3_1 {
|
|
/delete-property/ qcom,msm-bus,num-paths;
|
|
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
|
qcom,iommu-dma = "bypass";
|
|
};
|
|
|
|
&qupv3_2 {
|
|
/delete-property/ qcom,msm-bus,num-paths;
|
|
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
|
qcom,iommu-dma = "bypass";
|
|
};
|
|
|
|
&qupv3_3 {
|
|
/delete-property/ qcom,msm-bus,num-paths;
|
|
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
|
qcom,iommu-dma = "bypass";
|
|
};
|
|
|
|
&pcie_rc0 {
|
|
cnss_pci: cnss_pci {
|
|
reg = <0 0 0 0 0>;
|
|
qcom,iommu-group = <&cnss_pci_iommu_group>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cnss_pci_iommu_group: cnss_pci_iommu_group {
|
|
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-faults = "stall-disable", "no-CFRE",
|
|
"non-fatal";
|
|
};
|
|
};
|
|
};
|