mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-09 04:12:08 -05:00
98697c2d65
Add sa8195 vidc nodes and update smmu SIDs for sa8195-v2. Change-Id: I9c597ec04e9e05f43446f94283b95baa7ee43989
129 lines
3.6 KiB
Devicetree
129 lines
3.6 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-scshrike.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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&soc {
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msm_vidc: qcom,vidc@aa00000 {
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compatible = "qcom,msm-vidc", "qcom,scshrike-vidc";
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status = "ok"
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reg = <0xaa00000 0x200000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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/* IOMMU Config */
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#address-cells = <1>;
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#size-cells = <1>;
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/* LLCC Info */
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cache-slice-names = "vidsc0", "vidsc1";
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/* Supply */
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iris-ctl-supply = <&mvsc_gdsc>;
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vcodec-supply = <&mvs0_gdsc>;
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axic", "gcc_video_axi0",
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"gcc_video_axi1", "core_clk", "vcodec_clk",
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"cvp_clk";
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clocks = <&gcc GCC_VIDEO_AXIC_CLK>,
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<&gcc GCC_VIDEO_AXI0_CLK>,
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<&gcc GCC_VIDEO_AXI1_CLK>,
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<&videocc VIDEO_CC_MVSC_CORE_CLK>,
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<&videocc VIDEO_CC_MVS0_CORE_CLK>,
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<&videocc VIDEO_CC_MVS1_CORE_CLK>;
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qcom,proxy-clock-names = "gcc_video_axic",
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"gcc_video_axi0", "gcc_video_axi1",
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"core_clk", "vcodec_clk", "cvp_clk";
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resets = <&gcc GCC_VIDEO_AXIC_CLK_BCR>,
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<&videocc VIDEO_CC_MVSC_CORE_CLK_BCR>,
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<&gcc GCC_VIDEO_AXI0_CLK_BCR>,
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<&gcc GCC_VIDEO_AXI1_CLK_BCR>;
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reset-names = "video_axi_reset", "video_core_reset",
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"video_axi0_reset", "video_axi1_reset";
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qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1>;
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qcom,allowed-clock-rates = <225000000 300000000
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365000000 432000000 480000000>;
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/* Bus Interconnects */
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interconnect-names = "venus-cnoc", "venus-ddr", "venus-arm9-ddr", "venus-llcc";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_VENUS_CFG>,
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<&mc_virt MASTER_LLCC
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&mc_virt SLAVE_EBI1>,
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<&mmss_noc MASTER_VIDEO_P0
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&mc_virt SLAVE_EBI1>,
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<&mmss_noc MASTER_VIDEO_P0
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&gem_noc SLAVE_LLCC>;
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/* Bus BW range (low, high) for each bus */
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qcom,bus-range-kbps = <1000 1000
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1000 6533000
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1000 1000
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1000 6533000>;
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus =
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<&apps_smmu 0x1300 0x60>;
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x25800000 0xba800000>;
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dma-coherent-hint-cached;
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};
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secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus =
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<&apps_smmu 0x1304 0x60>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
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buffer-types = <0x480>;
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virtual-addr-pool = <0x1000000 0x24800000>;
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qcom,secure-context-bank;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus =
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<&apps_smmu 0x1301 0x4>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
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buffer-types = <0x241>;
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virtual-addr-pool = <0x500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus =
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<&apps_smmu 0x1303 0x20>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-pagetable = "LLC";
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qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
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buffer-types = <0x106>;
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virtual-addr-pool = <0x500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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/* Memory Heaps */
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qcom,msm-vidc,mem_cdsp {
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compatible = "qcom,msm-vidc,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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};
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