mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
40526282ad
PMIC PM8008 LDOs do not support low power mode (LPM). If configured for LPM, these LDOs continue to operate in normal power mode (NPM) with the same quiescent current but a reduced over-current protection (OCP) threshold, which can result in OCP triggering. Fix all PM8008 LDOs to use normal power mode (NPM) alone to avoid this. Change-Id: I2c8961eaba0677768da09aeba577a32810c1d50f
1316 lines
28 KiB
Devicetree
1316 lines
28 KiB
Devicetree
#include <dt-bindings/sound/qcom,gpr.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/spmi/spmi.h>
|
|
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. SCUBA";
|
|
compatible = "qcom,scuba";
|
|
qcom,msm-id = <441 0x10000>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
|
|
|
mem-offline {
|
|
compatible = "qcom,mem-offline";
|
|
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
|
|
<0x1 0xc0000000 0x0 0x80000000>,
|
|
<0x2 0xc0000000 0x1 0x40000000>;
|
|
granule = <512>;
|
|
};
|
|
|
|
aliases {
|
|
swr0 = &swr0;
|
|
swr1 = &swr1;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,armv8";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_0>;
|
|
L2_0: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
};
|
|
|
|
L1_I_0: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_0: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,armv8";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_0>;
|
|
|
|
L1_I_1: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_1: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,armv8";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_0>;
|
|
|
|
L1_I_2: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_2: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,armv8";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_0>;
|
|
|
|
L1_I_3: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_3: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <&CPU3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
firmware: firmware {
|
|
android {
|
|
compatible = "android,firmware";
|
|
vbmeta {
|
|
compatible="android,vbmeta";
|
|
parts = "vbmeta,boot,system,vendor,dtbo,recovery";
|
|
};
|
|
|
|
fstab {
|
|
compatible = "android,fstab";
|
|
vendor {
|
|
compatible = "android,vendor";
|
|
dev =
|
|
"/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
|
|
type = "ext4";
|
|
mnt_flags = "ro,barrier=1,discard";
|
|
fsmgr_flags = "wait,slotselect,avb";
|
|
status = "ok"
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
hyp_region: hyp_region@45700000 {
|
|
no-map;
|
|
reg = <0x0 0x45700000 0x0 0x600000>;
|
|
};
|
|
|
|
xbl_aop_mem: xbl_aop_mem@45e00000 {
|
|
no-map;
|
|
reg = <0x0 0x45e00000 0x0 0x100000>;
|
|
};
|
|
|
|
sec_apps_mem: sec_apps_region@45fff000 {
|
|
no-map;
|
|
reg = <0x0 0x45fff000 0x0 0x1000>;
|
|
};
|
|
|
|
smem_region: smem@46000000 {
|
|
no-map;
|
|
reg = <0x0 0x46000000 0x0 0x200000>;
|
|
};
|
|
|
|
pil_modem_mem: modem_region@4ab00000 {
|
|
no-map;
|
|
reg = <0x0 0x4ab00000 0x0 0x6900000>;
|
|
};
|
|
|
|
pil_video_mem: pil_video_region@51400000 {
|
|
no-map;
|
|
reg = <0x0 0x51400000 0x0 0x500000>;
|
|
};
|
|
|
|
wlan_msa_mem: wlan_msa_region@51900000 {
|
|
no-map;
|
|
reg = <0x0 0x51900000 0x0 0x100000>;
|
|
};
|
|
|
|
pil_adsp_mem: adsp_regions@51a00000 {
|
|
no-map;
|
|
reg = <0x0 0x51a00000 0x0 0x1c00000>;
|
|
};
|
|
|
|
pil_ipa_fw_mem: ips_fw_region@53600000 {
|
|
no-map;
|
|
reg = <0x0 0x53600000 0x0 0x10000>;
|
|
};
|
|
|
|
pil_ipa_gsi_mem: ipa_gsi_region@53610000 {
|
|
no-map;
|
|
reg = <0x0 0x53610000 0x0 0x5000>;
|
|
};
|
|
|
|
pil_gpu_mem: gpu_region@53615000 {
|
|
no-map;
|
|
reg = <0x0 0x53615000 0x0 0x2000>;
|
|
};
|
|
|
|
removed_region: removed_region@60000000 {
|
|
no-map;
|
|
reg = <0x0 0x60000000 0x0 0x3900000>;
|
|
};
|
|
|
|
adsp_mem: adsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x800000>;
|
|
};
|
|
|
|
dump_mem: mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
size = <0 0x800000>;
|
|
};
|
|
|
|
secure_display_memory: secure_display_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x5c00000>;
|
|
};
|
|
|
|
cont_splash_memory: cont_splash_region@5c000000 {
|
|
reg = <0x0 0x5c000000 0x0 0x00f00000>;
|
|
label = "cont_splash_region";
|
|
};
|
|
|
|
dfps_data_memory: dfps_data_region@5cf00000 {
|
|
reg = <0x0 0x5cf00000 0x0 0x0100000>;
|
|
label = "dfps_data_region";
|
|
};
|
|
|
|
disp_rdump_memory: disp_rdump_region@5c000000 {
|
|
reg = <0x0 0x5c000000 0x0 0x00f00000>;
|
|
label = "disp_rdump_region";
|
|
};
|
|
|
|
qseecom_mem: qseecom_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1400000>;
|
|
};
|
|
|
|
qseecom_ta_mem: qseecom_ta_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
/* global autoconfigured region for contiguous allocations */
|
|
linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
|
|
};
|
|
|
|
soc: soc { };
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@f200000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&intc>;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0xf200000 0x10000>, /* GICD */
|
|
<0xf300000 0x100000>; /* GICR * 8 */
|
|
interrupts = <1 9 4>;
|
|
};
|
|
|
|
wakegic: wake-gic {
|
|
compatible = "qcom,mpm-gic-scuba", "qcom,mpm";
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
|
|
reg = <0x45f01b8 0x1000>,
|
|
<0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */
|
|
reg-names = "vmpm", "ipc";
|
|
qcom,num-mpm-irqs = <96>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&intc>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 1 0xf08>,
|
|
<1 2 0xf08>,
|
|
<1 3 0xf08>,
|
|
<1 0 0xf08>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
|
|
timer@f120000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0xf120000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@f121000 {
|
|
frame-number = <0>;
|
|
interrupts = <0 8 0x4>,
|
|
<0 7 0x4>;
|
|
reg = <0xf121000 0x1000>,
|
|
<0xf122000 0x1000>;
|
|
};
|
|
|
|
frame@f123000 {
|
|
frame-number = <1>;
|
|
interrupts = <0 9 0x4>;
|
|
reg = <0xf123000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f124000 {
|
|
frame-number = <2>;
|
|
interrupts = <0 10 0x4>;
|
|
reg = <0xf124000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f125000 {
|
|
frame-number = <3>;
|
|
interrupts = <0 11 0x4>;
|
|
reg = <0xf125000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f126000 {
|
|
frame-number = <4>;
|
|
interrupts = <0 12 0x4>;
|
|
reg = <0xf126000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f127000 {
|
|
frame-number = <5>;
|
|
interrupts = <0 13 0x4>;
|
|
reg = <0xf127000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f128000 {
|
|
frame-number = <6>;
|
|
interrupts = <0 14 0x4>;
|
|
reg = <0xf128000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,msm-imem@c125000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0xc125000 0x1000>;
|
|
ranges = <0x0 0xc125000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
restart@440b000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0x440b000 0x4>,
|
|
<0x03d3000 0x4>;
|
|
reg-names = "pshold-base", "tcsr-boot-misc-detect";
|
|
status="disabled";
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@4403000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0x4403000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
status="disabled";
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
status="disabled";
|
|
};
|
|
|
|
qcom,chd_silver {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "silver";
|
|
qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
|
|
0x0f1a80b0 0x0f1b80b0>;
|
|
qcom,config-arr = <0x0f1880b8 0x0f1980b8
|
|
0x0f1a80b8 0x0f1b80b8>;
|
|
|
|
status="disabled";
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x280000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
qcom,guard-memory;
|
|
};
|
|
|
|
thermal_zones: thermal-zones { };
|
|
|
|
qfprom: qfprom@1b40000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x1b40000 0x7000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
read-only;
|
|
ranges;
|
|
status="disabled";
|
|
feat_conf5: feat_conf5@6018 {
|
|
reg = <0x6018 0x4>;
|
|
};
|
|
|
|
adsp_variant: adsp_variant@6011 {
|
|
reg = <0x6011 0x1>;
|
|
bits = <3 1>;
|
|
};
|
|
|
|
};
|
|
|
|
wdog: qcom,wdt@f017000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0xf017000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <9360>;
|
|
qcom,ipi-ping;
|
|
qcom,wakeup-enable;
|
|
};
|
|
|
|
dcc: dcc_v2@1be2000 {
|
|
compatible = "qcom,dcc-v2";
|
|
reg = <0x1be2000 0x1000>,
|
|
<0x1bee000 0x2000>;
|
|
reg-names = "dcc-base", "dcc-ram-base";
|
|
dcc-ram-offset = <0x2000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rpm_bus: qcom,rpm-smd {
|
|
compatible = "qcom,rpm-smd";
|
|
rpm-channel-name = "rpm_requests";
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
|
|
rpm-channel-type = <15>; /* SMD_APPS_RPM */
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <&dump_mem>;
|
|
|
|
c0_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x0>;
|
|
};
|
|
|
|
c1_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x1>;
|
|
};
|
|
|
|
c2_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x2>;
|
|
};
|
|
|
|
c3_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x3>;
|
|
};
|
|
|
|
l1_icache0 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
l1_icache1 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
l1_icache2 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
l1_icache3 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
l1_dcache0 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
l1_dcache1 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
l1_dcache2 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
l1_dcache3 {
|
|
qcom,dump-size = <0x9040>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
l2_tlb0 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
l2_tlb1 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
l2_tlb2 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x122>;
|
|
};
|
|
|
|
l2_tlb3 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x123>;
|
|
};
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@1c40000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x1c40000 0x1100>,
|
|
<0x1e00000 0x2000000>,
|
|
<0x3e00000 0x100000>,
|
|
<0x3f00000 0xa0000>,
|
|
<0x1c0a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@00340000 {
|
|
compatible = "syscon";
|
|
reg = <0x340000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_region>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
rpm_msg_ram: memory@045f0000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0x45f0000 0x7000>;
|
|
};
|
|
|
|
apcs_glb: mailbox@0f111000 {
|
|
compatible = "qcom,scuba-apcs-hmss-global";
|
|
reg = <0xF111000 0x1000>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem>;
|
|
restrict-access;
|
|
};
|
|
|
|
qcom,msm_fastrpc {
|
|
compatible = "qcom,msm-fastrpc-compute";
|
|
qcom,rpc-latency-us = <611>;
|
|
qcom,adsp-remoteheap-vmid = <22 37>;
|
|
qcom,fastrpc-adsp-audio-pdr;
|
|
qcom,fastrpc-adsp-sensors-pdr;
|
|
|
|
qcom,msm_fastrpc_compute_cb1 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x01C3 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb2 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x01C4 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb3 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x01C5 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb4 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x01C6 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb5 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x01C7 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
};
|
|
|
|
};
|
|
|
|
rpm-glink {
|
|
compatible = "qcom,glink-rpm";
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
|
mboxes = <&apcs_glb 0>;
|
|
|
|
qcom,rpm_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>,
|
|
<&glink_adsp>;
|
|
};
|
|
|
|
};
|
|
|
|
pil_scm_pas {
|
|
compatible = "qcom,pil-tz-scm-pas";
|
|
interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
|
|
};
|
|
|
|
qcom,lpass@ab00000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0xab00000 0x00100>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
|
|
vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>;
|
|
qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>;
|
|
qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
|
|
|
|
qcom,firmware-name = "adsp";
|
|
memory-region = <&pil_adsp_mem>;
|
|
qcom,proxy-timeout-ms = <10000>;
|
|
qcom,sysmon-id = <1>;
|
|
qcom,minidump-id = <5>;
|
|
qcom,ssctl-instance-id = <0x14>;
|
|
qcom,pas-id = <1>;
|
|
qcom,smem-id = <423>;
|
|
qcom,complete-ramdump;
|
|
qcom,minidump-as-elf32;
|
|
|
|
/* Inputs from lpass */
|
|
interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&adsp_smp2p_in 0 0>,
|
|
<&adsp_smp2p_in 2 0>,
|
|
<&adsp_smp2p_in 1 0>,
|
|
<&adsp_smp2p_in 3 0>;
|
|
|
|
interrupt-names = "qcom,wdog",
|
|
"qcom,err-fatal",
|
|
"qcom,proxy-unvote",
|
|
"qcom,err-ready",
|
|
"qcom,stop-ack";
|
|
|
|
/* Outputs to lpass */
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "qcom,force-stop";
|
|
};
|
|
|
|
pil_modem: qcom,mss@6080000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x6080000 0x100>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
qcom,proxy-reg-names = "vdd_cx";
|
|
|
|
qcom,firmware-name = "modem";
|
|
memory-region = <&pil_modem_mem>;
|
|
qcom,proxy-timeout-ms = <10000>;
|
|
qcom,sysmon-id = <0>;
|
|
qcom,ssctl-instance-id = <0x12>;
|
|
qcom,pas-id = <4>;
|
|
qcom,smem-id = <421>;
|
|
qcom,minidump-id = <3>;
|
|
qcom,aux-minidump-ids = <4>;
|
|
qcom,complete-ramdump;
|
|
qcom,sequential-fw-load;
|
|
|
|
/* Inputs from mss */
|
|
interrupts-extended = <&intc 0 307 1>,
|
|
<&modem_smp2p_in 0 0>,
|
|
<&modem_smp2p_in 2 0>,
|
|
<&modem_smp2p_in 1 0>,
|
|
<&modem_smp2p_in 3 0>,
|
|
<&modem_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "qcom,wdog",
|
|
"qcom,err-fatal",
|
|
"qcom,proxy-unvote",
|
|
"qcom,err-ready",
|
|
"qcom,stop-ack",
|
|
"qcom,shutdown-ack";
|
|
|
|
/* Outputs to mss */
|
|
qcom,smem-states = <&modem_smp2p_out 0>;
|
|
qcom,smem-state-names = "qcom,force-stop";
|
|
};
|
|
|
|
qcom_scm: qcomscm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 12>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 2>;
|
|
};
|
|
|
|
qcom,modem_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_adsp>;
|
|
};
|
|
};
|
|
|
|
glink_adsp: adsp {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 8>;
|
|
mbox-names = "adsp_smem";
|
|
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
audio_gpr: qcom,gpr {
|
|
compatible = "qcom,gpr";
|
|
qcom,glink-channels = "adsp_apps";
|
|
qcom,intents = <0x200 20>;
|
|
reg = <GPR_DOMAIN_ADSP>;
|
|
spf_core {
|
|
compatible = "qcom,spf_core";
|
|
reg = <GPR_SVC_ADSP_CORE>;
|
|
};
|
|
|
|
audio-pkt {
|
|
compatible = "qcom,audio-pkt";
|
|
qcom,audiopkt-ch-name = "apr_audio_svc";
|
|
reg = <GPR_SVC_MAX>;
|
|
};
|
|
|
|
audio_prm: q6prm {
|
|
compatible = "qcom,audio_prm";
|
|
reg = <GPR_SVC_ASM>;
|
|
};
|
|
};
|
|
|
|
qcom,adsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
|
|
qcom,entry-name = "wlan";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 10>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
slim_aud: slim@a5c0000 {
|
|
cell-index = <1>;
|
|
compatible = "qcom,slim-ngd";
|
|
reg = <0xa5c0000 0x2c000>,
|
|
<0xa584000 0x20000>, <0xa66e000 0x2000>;
|
|
reg-names = "slimbus_physical",
|
|
"slimbus_bam_physical","slimbus_lpass_mem";
|
|
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
|
|
qcom,apps-ch-pipes = <0x0>;
|
|
qcom,ea-pc = <0x360>;
|
|
status = "ok"
|
|
};
|
|
qcom,venus@5ab0000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x5ab0000 0x20000>;
|
|
|
|
vdd-supply = <&gcc_venus_gdsc>;
|
|
qcom,proxy-reg-names = "vdd";
|
|
|
|
clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
|
|
<&gcc GCC_VENUS_CTL_AXI_CLK>,
|
|
<&gcc GCC_VIDEO_AHB_CLK>,
|
|
<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
|
|
clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
|
|
qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
|
|
|
|
qcom,core-freq = <240000000>;
|
|
qcom,ahb-freq = <240000000>;
|
|
|
|
qcom,pas-id = <9>;
|
|
interconnect-names = "pil-venus";
|
|
interconnects = <&mmnrt_virt MASTER_VIDEO_P0
|
|
&bimc SLAVE_EBI_CH0>;
|
|
qcom,proxy-timeout-ms = <100>;
|
|
qcom,firmware-name = "venus";
|
|
memory-region = <&pil_video_mem>;
|
|
};
|
|
|
|
icnss: qcom,icnss@C800000 {
|
|
compatible = "qcom,icnss";
|
|
reg = <0xC800000 0x800000>,
|
|
<0xb0000000 0x10000>;
|
|
reg-names = "membase", "smmu_iova_ipa";
|
|
iommus = <&apps_smmu 0x1A0 0x1>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
|
|
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
|
|
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
|
|
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
|
|
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
|
|
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
|
|
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
|
|
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
|
|
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
|
|
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
|
|
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
|
|
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
|
|
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
|
|
vdd-cx-mx-supply = <&L7A>;
|
|
vdd-1.8-xo-supply = <&L13A>;
|
|
vdd-1.3-rfa-supply = <&L10A>;
|
|
vdd-3.3-ch0-supply = <&L22A>;
|
|
qcom,vdd-cx-mx-config = <640000 640000>;
|
|
qcom,vdd-3.3-ch0-config = <3000000 3312000>;
|
|
qcom,smp2p_map_wlan_1_in {
|
|
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
|
|
<&smp2p_wlan_1_in 1 0>;
|
|
interrupt-names = "qcom,smp2p-force-fatal-error",
|
|
"qcom,smp2p-early-crash-ind";
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "pm2250.dtsi"
|
|
#include "pm2250-rpm-regulator.dtsi"
|
|
#include "scuba-regulator.dtsi"
|
|
#include "scuba-iot-pinctrl.dtsi"
|
|
#include "scuba-ion.dtsi"
|
|
#include "msm-arm-smmu-scuba.dtsi"
|
|
#include "scuba-audio.dtsi"
|
|
#include "scuba-vidc.dtsi"
|
|
|
|
&qupv3_se1_i2c {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "ok"
|
|
|
|
pm8008_8: qcom,pm8008@8 {
|
|
compatible = "qcom,i2c-pmic";
|
|
reg = <0x8>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pm8008_active>;
|
|
|
|
pm8008_chip: qcom,pm8008-chip@900 {
|
|
compatible = "qcom,pm8008-chip";
|
|
reg = <0x900>;
|
|
|
|
PM8008_EN: qcom,pm8008-chip-en {
|
|
regulator-name = "pm8008-chip-en";
|
|
};
|
|
};
|
|
|
|
qcom,revid@100 {
|
|
compatible = "qcom,qpnp-revid";
|
|
reg = <0x100>;
|
|
};
|
|
};
|
|
|
|
pm8008_9: qcom,pm8008@9 {
|
|
compatible = "qcom,i2c-pmic";
|
|
reg = <0x9>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pm8008_regulators: qcom,pm8008-regulator {
|
|
compatible = "qcom,pm8008-regulator";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pm8008_en-supply = <&PM8008_EN>;
|
|
|
|
vdd_l1_l2-supply = <&S3A>;
|
|
|
|
L1P: qcom,pm8008-l1@4000 {
|
|
reg = <0x4000>;
|
|
regulator-name = "pm8008_l1";
|
|
regulator-min-microvolt = <528000>;
|
|
regulator-max-microvolt = <1256000>;
|
|
qcom,min-dropout-voltage = <75000>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
|
|
L2P: qcom,pm8008-l2@4100 {
|
|
reg = <0x4100>;
|
|
regulator-name = "pm8008_l2";
|
|
regulator-min-microvolt = <528000>;
|
|
regulator-max-microvolt = <1144000>;
|
|
qcom,min-dropout-voltage = <187500>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
|
|
L3P: qcom,pm8008-l3@4200 {
|
|
reg = <0x4200>;
|
|
regulator-name = "pm8008_l3";
|
|
regulator-min-microvolt = <2704000>;
|
|
regulator-max-microvolt = <2896000>;
|
|
qcom,min-dropout-voltage = <200000>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
|
|
L4P: qcom,pm8008-l4@4300 {
|
|
reg = <0x4300>;
|
|
regulator-name = "pm8008_l4";
|
|
regulator-min-microvolt = <2704000>;
|
|
regulator-max-microvolt = <2896000>;
|
|
qcom,min-dropout-voltage = <200000>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
|
|
L5P: qcom,pm8008-l5@4400 {
|
|
reg = <0x4400>;
|
|
regulator-name = "pm8008_l5";
|
|
regulator-min-microvolt = <2704000>;
|
|
regulator-max-microvolt = <2896000>;
|
|
qcom,min-dropout-voltage = <300000>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
|
|
L6P: qcom,pm8008-l6@4500 {
|
|
reg = <0x4500>;
|
|
regulator-name = "pm8008_l6";
|
|
regulator-min-microvolt = <2704000>;
|
|
regulator-max-microvolt = <2896000>;
|
|
qcom,min-dropout-voltage = <300000>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
|
|
L7P: qcom,pm8008-l7@4600 {
|
|
reg = <0x4600>;
|
|
regulator-name = "pm8008_l7";
|
|
regulator-min-microvolt = <1656000>;
|
|
regulator-max-microvolt = <1896000>;
|
|
qcom,min-dropout-voltage = <300000>;
|
|
qcom,hpm-min-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pm2250_vadc {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&conn_therm_default &skin_therm_default>;
|
|
|
|
xo_therm {
|
|
reg = <ADC5_XO_THERM_100K_PU>;
|
|
label = "xo_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
pa_therm {
|
|
reg = <ADC5_AMUX_THM1_100K_PU>;
|
|
label = "pa_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
quiet_therm {
|
|
reg = <ADC5_AMUX_THM2_100K_PU>;
|
|
label = "quiet_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
msm_therm {
|
|
reg = <ADC5_AMUX_THM3_100K_PU>;
|
|
label = "msm_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
skin_therm {
|
|
reg = <ADC5_GPIO3_100K_PU>;
|
|
label = "skin_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
conn_therm {
|
|
reg = <ADC5_GPIO4_100K_PU>;
|
|
label = "conn_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
};
|
|
|
|
&pm2250_gpios {
|
|
skin_therm {
|
|
skin_therm_default: skin_therm_default {
|
|
pins = "gpio5";
|
|
bias-high-impedance;
|
|
};
|
|
};
|
|
|
|
conn_therm {
|
|
conn_therm_default: conn_therm_default {
|
|
pins = "gpio6";
|
|
bias-high-impedance;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spmi_bus {
|
|
qcom,pm2250@0 {
|
|
pm2250_adc_tm_iio: adc_tm@3400 {
|
|
compatible = "qcom,adc-tm5-iio";
|
|
reg = <0x3400 0x100>;
|
|
#thermal-sensor-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>,
|
|
<&pm2250_vadc ADC5_AMUX_THM1_100K_PU>,
|
|
<&pm2250_vadc ADC5_AMUX_THM2_100K_PU>,
|
|
<&pm2250_vadc ADC5_AMUX_THM3_100K_PU>,
|
|
<&pm2250_vadc ADC5_GPIO3_100K_PU>,
|
|
<&pm2250_vadc ADC5_GPIO4_100K_PU>,
|
|
<&pm2250_vadc ADC5_SBUx>;
|
|
|
|
xo_therm {
|
|
reg = <ADC5_XO_THERM_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
pa_therm {
|
|
reg = <ADC5_AMUX_THM1_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
quiet_therm {
|
|
reg = <ADC5_AMUX_THM2_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
msm_therm {
|
|
reg = <ADC5_AMUX_THM3_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
skin_therm {
|
|
reg = <ADC5_GPIO3_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
conn_therm {
|
|
reg = <ADC5_GPIO4_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
s3_die_temp {
|
|
reg = <ADC5_SBUx>;
|
|
};
|
|
};
|
|
};
|
|
};
|