mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
60a6dd1952
Add BOOT_CONFIG to support the EDL over PCIe for sdxlemur. Change-Id: Ia33b56d3bbb4e4bf4df1f6ac049b5b85d1938c5a
180 lines
4.4 KiB
Devicetree
180 lines
4.4 KiB
Devicetree
#include "sdxlemur.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR V2";
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compatible = "qcom,sdxlemur";
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qcom,msm-id = <458 0x20000>, <483 0x20000>, <509 0x20000>;
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};
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/* Overriding the BAM node to enable SMMU S1 support in sdxlemur V2
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* Adding i2c SID's in BAM node, as descriptors buffers for i2c
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* usecase are allocated in BAM DMA driver.
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*/
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&dma_blsp1 {
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iommus = <&apps_smmu 0x148 0x1>,
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<&apps_smmu 0x14a 0x1>,
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<&apps_smmu 0x14c 0x1>,
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<&apps_smmu 0x14e 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_1 {
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iommus = <&apps_smmu 0x148 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_2 {
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iommus = <&apps_smmu 0x14a 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_3 {
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iommus = <&apps_smmu 0x14c 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_4 {
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iommus = <&apps_smmu 0x14e 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_5 {
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iommus = <&apps_smmu 0x148 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_6 {
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iommus = <&apps_smmu 0x14a 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&i2c_7 {
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iommus = <&apps_smmu 0x14e 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&spi_1 {
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iommus = <&apps_smmu 0x148 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&spi_2 {
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iommus = <&apps_smmu 0x14a 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&spi_3 {
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iommus = <&apps_smmu 0x14c 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&spi_4 {
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iommus = <&apps_smmu 0x14e 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart1a_hs {
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iommus = <&apps_smmu 0x140 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart1b_hs {
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iommus = <&apps_smmu 0x140 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart2a_hs {
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iommus = <&apps_smmu 0x142 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart2b_hs {
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iommus = <&apps_smmu 0x142 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart3_hs {
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iommus = <&apps_smmu 0x144 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart4a_hs {
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iommus = <&apps_smmu 0x146 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&blsp1_uart4b_hs {
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iommus = <&apps_smmu 0x146 0x1>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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};
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&apsscc {
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qcom,speed0-bin-v0 =
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< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
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< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
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< 1804800000 RPMH_REGULATOR_LEVEL_TURBO>;
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};
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&cpufreq {
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qcom,cpufreq-table =
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< 345600 >,
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< 576000 >,
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< 1094400 >,
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< 1804800 >;
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};
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&cpu0_cpu_ddr_tbl {
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qcom,core-dev-table =
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< 345600 MHZ_TO_MBPS( 300, 4) >,
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< 576000 MHZ_TO_MBPS( 768, 4) >,
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< 1440000 MHZ_TO_MBPS(1555, 4) >,
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< 1804800 MHZ_TO_MBPS(2092, 4) >;
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};
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&pil_modem {
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qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
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};
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&dload_mode {
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qcom,boot-config-shift = <1 4>;
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};
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