mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
84a95d00e0
Fix compilation warnings for sa8155, sa8195 and sa6155. Change-Id: I6463b9106e2c40104720052b073455164e641df1
654 lines
15 KiB
Devicetree
654 lines
15 KiB
Devicetree
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#define KHZ_TO_KBPS(khz, w) ((khz * 1000 * w) / (1024))
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a612_zap";
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memory-region = <&pil_gpu_mem>;
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};
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msm_gpu: qcom,kgsl-3d0@5000000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok"
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reg = <0x5000000 0x90000>,
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<0x780000 0x6fff>;
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reg-names = "kgsl_3d0_reg_memory",
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"qfprom_memory";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x06010200>;
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qcom,initial-pwrlevel = <5>;
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/* <HZ/12> */
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qcom,idle-timeout = <80>;
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qcom,no-nap;
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qcom,highest-bank-bit = <14>;
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qcom,ubwc-mode = <2>;
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qcom,min-access-length = <32>;
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/* base addr, size */
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
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#cooling-cells = <2>;
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clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>;
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clock-names = "core_clk", "rbbmtimer_clk", "gcc_gpu_axi_clk",
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"iface_clk", "gcc_gpu_memnoc_gfx",
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"gpu_cc_hlos1_vote_gpu_smmu", "gmu_clk";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-ddr =
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<KHZ_TO_KBPS(0, 4)>, /* index=0 */
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<KHZ_TO_KBPS(100000, 4)>, /* index=1 (Low SVS) */
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<KHZ_TO_KBPS(200000, 4)>, /* index=2 (Low SVS) */
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<KHZ_TO_KBPS(300000, 4)>, /* index=3 (Low SVS) */
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<KHZ_TO_KBPS(451200, 4)>, /* index=4 (Low SVS) */
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<KHZ_TO_KBPS(547200, 4)>, /* index=5 (Low SVS) */
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<KHZ_TO_KBPS(681600, 4)>, /* index=6 (SVS) */
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<KHZ_TO_KBPS(768000, 4)>, /* index=7 (SVS) */
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<KHZ_TO_KBPS(1017600, 4)>, /* index=8 (SVS L1) */
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<KHZ_TO_KBPS(1353600, 4)>, /* index=9 (NOM) */
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<KHZ_TO_KBPS(1555200, 4)>, /* index=10 (NOM) */
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<KHZ_TO_KBPS(1804800, 4)>; /* index=11 (TURBO) */
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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/* CPU latency parameter */
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qcom,pm-qos-active-latency = <67>;
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qcom,pm-qos-wakeup-latency = <67>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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/* Context aware jump target power level */
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qcom,ca-target-pwrlevel = <3>;
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qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>;
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/*
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* Speed-bin zero is default speed bin.
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* For rest of the speed bins, speed-bin value
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* is calulated as FMAX/4.8 MHz round up to zero
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* decimal places.
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*/
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible="qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <5>;
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qcom,ca-target-pwrlevel = <3>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <845000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* NOM L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <745000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <700000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS L1 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <550000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <435000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <290000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <4>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <177>;
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qcom,initial-pwrlevel = <5>;
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qcom,ca-target-pwrlevel = <3>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <845000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* NOM L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <745000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <700000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS L1 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <550000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <435000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <290000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <4>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <187>;
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qcom,initial-pwrlevel = <6>;
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qcom,ca-target-pwrlevel = <4>;
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/* TURBO L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <895000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <845000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* NOM L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <745000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <700000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <550000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <435000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <290000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <4>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-3 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <156>;
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qcom,initial-pwrlevel = <4>;
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qcom,ca-target-pwrlevel = <2>;
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/* NOM L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <745000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <700000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <550000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <435000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <290000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <4>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-4 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <136>;
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qcom,initial-pwrlevel = <3>;
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qcom,ca-target-pwrlevel = <1>;
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/* NOM */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <550000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <435000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <7>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <8>;
|
|
};
|
|
|
|
/* Low SVS */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <290000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
qcom,bus-freq = <4>;
|
|
qcom,bus-min = <4>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <105>;
|
|
|
|
qcom,initial-pwrlevel = <1>;
|
|
qcom,ca-target-pwrlevel = <2>;
|
|
|
|
/* SVS L1 */
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <500000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <7>;
|
|
qcom,bus-max = <9>;
|
|
};
|
|
|
|
/* SVS */
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <435000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
qcom,bus-freq = <7>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <8>;
|
|
};
|
|
|
|
/* Low SVS */
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <290000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
qcom,bus-freq = <4>;
|
|
qcom,bus-min = <4>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <73>;
|
|
|
|
qcom,initial-pwrlevel = <1>;
|
|
qcom,ca-target-pwrlevel = <0>;
|
|
|
|
/* SVS */
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <350000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
qcom,bus-freq = <7>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <8>;
|
|
};
|
|
|
|
/* Low SVS */
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <290000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
qcom,bus-freq = <4>;
|
|
qcom,bus-min = <4>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
kgsl_msm_iommu: qcom,kgsl-iommu@50a0000 {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
|
|
reg = <0x50a0000 0x10000>;
|
|
|
|
gfx3d_user: gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_user";
|
|
iommus = <&kgsl_smmu 0x0 0x401>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
|
|
gfx3d_secure: gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_secure";
|
|
iommus = <&kgsl_smmu 0x2 0x400>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
};
|
|
|
|
rgmu: qcom,rgmu@0x0506d000 {
|
|
label = "kgsl-rgmu";
|
|
compatible = "qcom,gpu-rgmu";
|
|
|
|
reg = <0x506d000 0x31000>;
|
|
reg-names = "kgsl_rgmu";
|
|
|
|
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "kgsl_oob", "kgsl_rgmu";
|
|
|
|
regulator-names = "vddcx", "vdd";
|
|
vddcx-supply = <&gpu_cx_gdsc>;
|
|
vdd-supply = <&gpu_gx_gdsc>;
|
|
|
|
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_CXO_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
|
<&gpucc GPU_CC_GX_GFX3D_CLK>;
|
|
|
|
clock-names = "gmu", "rbbmtimer", "mem",
|
|
"iface", "mem_iface",
|
|
"smmu_vote", "core";
|
|
};
|
|
};
|