mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 01:51:34 -05:00
2b5e092fd3
- Add second supplier chipone icnl9911c. - def-build-id and def-config-id need to be updated. Change-Id: Iee330d44be94f3611c3d09a8ddedc179d378e3b7 Signed-off-by: wengjun1 <[email protected]> Reviewed-on: https://gerrit.mot.com/1809669 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Jianqiu Huang <[email protected]> Reviewed-by: Huosheng Liao <[email protected]> Submit-Approved: Jira Key
108 lines
2.4 KiB
Devicetree
Executable file
108 lines
2.4 KiB
Devicetree
Executable file
/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&qupv3_se0_i2c {
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status = "disabled";
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};
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&qupv3_se0_spi_pins {
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qupv3_se0_spi_active: qupv3_se0_spi_active {
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mux {
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pins = "gpio0", "gpio1", "gpio2";
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function = "qup00";
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};
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config {
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pins = "gpio0", "gpio1", "gpio2";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
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mux {
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pins = "gpio0", "gpio1", "gpio2";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1", "gpio2";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
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mux {
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pins = "gpio3";
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function = "qup00";
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};
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config {
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pins = "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_cs_sleep: qupv3_se0_spi_cs_sleep {
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mux {
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pins = "gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio3";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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};
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&qupv3_se0_spi {
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status = "ok"
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pinctrl-0 = <&qupv3_se0_spi_active &qupv3_se0_spi_cs_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep &qupv3_se0_spi_cs_sleep>;
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novatek@0{
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compatible = "novatek,NVT-ts-spi";
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reg = <0x0>;
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spi-max-frequency = <9600000>; /* 4800000,9600000,15000000,19200000 */
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novatek,reset-gpio = <&tlmm 21 0x00>;
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novatek,irq-gpio = <&tlmm 22 0x2001>;
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novatek,def-max-resolution = <720 1600>;
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novatek,swrst-n8-addr = <0x03F0FE>;
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novatek,spi-rd-fast-addr = <0x03F310>;
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novatek,report_gesture_key;
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panel = <&dsi_nt36525c_djn_video>;
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status = "ok"
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};
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chipone_tddi@1 {
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compatible = "chipone-tddi";
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reg = <0x1>;
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spi-max-frequency = <4800000>;
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interrupt-parent = <&tlmm>;
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interrupts = <22 0x2008>;
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spi-cpha;
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spi-cpol;
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chipone,rst-gpio = <&tlmm 21 0x00>;
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chipone,irq-gpio = <&tlmm 22 0x2008>;
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chipone,x-res = <720>;
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chipone,y-res = <1600>;
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chipone,def-build-id = <0x0101>;
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chipone,def-config-id = <0x0001>;
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panel = <&dsi_icnl9911c_tm_video>;
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status = "ok"
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};
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};
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