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Filename Latest commit message Latest commit date
Yujun Zhang 80d06ebb7c disp: pll: limit clock rate of shadow VCO clock
Limit clock rate of shadow VCO clock as normal VCO clock.
For larger bit clock rate gap between switched ones, the clock switching
would fail due to mismatched VCO clock rate between normal VCO clock and
shadow one.

Change-Id: I9d68725de360ac28c243a3ce1800bfb139f39757
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
2019-07-25 02:38:39 -07:00
config makefile: add LITO config support for display techpack 2019-05-07 23:35:59 -07:00
msm Merge "disp: msm: dsi: adding prefix for logs" 2019-07-23 01:20:03 -07:00
pll disp: pll: limit clock rate of shadow VCO clock 2019-07-25 02:38:39 -07:00
rotator Merge "msm/sde/rotator: Initialise rotator module after MDP module init" 2019-06-28 22:04:04 -07:00
Makefile makefile: add LITO config support for display techpack 2019-05-07 23:35:59 -07:00
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