mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
84a95d00e0
Fix compilation warnings for sa8155, sa8195 and sa6155. Change-Id: I6463b9106e2c40104720052b073455164e641df1
885 lines
26 KiB
Devicetree
885 lines
26 KiB
Devicetree
#include <dt-bindings/interconnect/qcom,scshrike.h>
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&soc {
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/* QUPv3 West Instances
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* West 0 : SE 0
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* West 1 : SE 1
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* West 2 : SE 2
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* West 3 : SE 3
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* West 4 : SE 4
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* West 5 : SE 5
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* West 6 : SE 6
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* West 7 : SE 7
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*
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* QUPv3 East0 and East1 Instances
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* East1 0 : SE 8
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* East1 1 : SE 9
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* East1 2 : SE 10
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* East1 3 : SE 11
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* East1 4 : SE 12
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* East1 5 : SE 16
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* East1 0 : SE 17
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* East0 1 : SE 18
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* East0 2 : SE 19
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* East0 3 : SE 13
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* East0 4 : SE 14
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* East0 5 : SE 15
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*/
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x8c0000 0x6000>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_0 SLAVE_EBI1>;
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iommus = <&apps_smmu 0x4c3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok"
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};
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/* I2C */
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qupv3_se0_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@884000 {
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compatible = "qcom,i2c-geni";
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reg = <0x884000 0x4000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@88c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x88c000 0x4000>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@890000 {
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compatible = "qcom,i2c-geni";
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reg = <0x890000 0x4000>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@894000 {
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compatible = "qcom,i2c-geni";
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reg = <0x894000 0x4000>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se6_i2c: i2c@898000 {
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compatible = "qcom,i2c-geni";
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reg = <0x898000 0x4000>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@89c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x89c000 0x4000>;
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_i2c_active>;
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pinctrl-1 = <&qupv3_se7_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* SPI */
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qupv3_se0_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_spi: spi@884000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x884000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_spi: spi@888000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x888000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_spi: spi@88c000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x88c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_spi_active>;
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pinctrl-1 = <&qupv3_se3_spi_sleep>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_spi: spi@890000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x890000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_spi_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_spi: spi@894000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x894000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_spi_active>;
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pinctrl-1 = <&qupv3_se5_spi_sleep>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se6_spi: spi@898000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x898000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_spi_active>;
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pinctrl-1 = <&qupv3_se6_spi_sleep>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se7_spi: spi@89c000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x89c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_spi_active>;
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pinctrl-1 = <&qupv3_se7_spi_sleep>;
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* QUPv3 East1 Instances */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0xac0000 0x6000>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_1 SLAVE_EBI1>;
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iommus = <&apps_smmu 0x603 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok"
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};
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qupv3_se4_4uart: qcom,qup_uart@890000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x890000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>,
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<&qupv3_se4_default_tx>;
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pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
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<&qupv3_se4_tx>;
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pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
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<&qupv3_se4_tx>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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qupv3_se10_2uart: qcom,qup_uart@a88000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0xa88000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_2uart_active>;
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pinctrl-1 = <&qupv3_se10_2uart_sleep>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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/* Debug UART Instance for CDP/MTP platform */
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qupv3_se12_2uart: qcom,qup_uart@a90000 {
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compatible = "qcom,msm-geni-console";
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reg = <0xa90000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se12_2uart_active>;
|
|
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 4-wire UART */
|
|
qupv3_se13_4uart: qcom,qup_uart@c8c000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0xc8c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "active", "sleep";
|
|
pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,
|
|
<&qupv3_se13_default_tx>;
|
|
pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
|
|
<&qupv3_se13_tx>;
|
|
pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
|
|
<&qupv3_se13_tx>;
|
|
interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&tlmm 46 0>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
qcom,wakeup-byte = <0xFD>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se16_2uart: qcom,qup_uart@a94000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0xa94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se16_2uart_active>;
|
|
pinctrl-1 = <&qupv3_se16_2uart_sleep>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C */
|
|
qupv3_se8_i2c: i2c@a80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se9_i2c: i2c@a84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se10_i2c: i2c@a88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se10_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se11_i2c: i2c@a8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se12_i2c: i2c@a90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se12_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SPI */
|
|
qupv3_se8_spi: spi@a80000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa80000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se8_spi_active>;
|
|
pinctrl-1 = <&qupv3_se8_spi_active>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se9_spi: spi@a84000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa84000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se9_spi_active>;
|
|
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se10_spi: spi@a88000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa88000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se10_spi_active>;
|
|
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se11_spi: spi@a8c000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa8c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_spi_active>;
|
|
pinctrl-1 = <&qupv3_se11_spi_sleep>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se12_spi: spi@a90000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa90000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se12_spi_active>;
|
|
pinctrl-1 = <&qupv3_se12_spi_sleep>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* QUPv3 East Instances */
|
|
qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
|
|
compatible = "qcom,qupv3-geni-se";
|
|
reg = <0xcc0000 0x6000>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-bus-ids =
|
|
<MASTER_QUP_2 SLAVE_EBI1>;
|
|
iommus = <&apps_smmu 0x7a3 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
status = "ok"
|
|
};
|
|
|
|
/* I2C */
|
|
qupv3_se13_i2c: i2c@c8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xc8c000 0x4000>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se13_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se14_i2c: i2c@c90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xc90000 0x4000>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se14_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se15_i2c: i2c@c94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xc94000 0x4000>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se15_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se16_i2c: i2c@a94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se16_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se16_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se17_i2c: i2c@c80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xc80000 0x4000>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se17_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se17_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se18_i2c: i2c@c84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xc84000 0x4000>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se18_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se18_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se19_i2c: i2c@c88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xc88000 0x4000>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se19_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se19_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SPI */
|
|
qupv3_se13_spi: spi@c8c000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xc8c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se13_spi_active>;
|
|
pinctrl-1 = <&qupv3_se13_spi_sleep>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se14_spi: spi@c90000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xc90000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se14_spi_active>;
|
|
pinctrl-1 = <&qupv3_se14_spi_sleep>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se15_spi: spi@c94000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xc94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se15_spi_active>;
|
|
pinctrl-1 = <&qupv3_se15_spi_sleep>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se16_spi: spi@a94000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se16_spi_active>;
|
|
pinctrl-1 = <&qupv3_se16_spi_sleep>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se17_spi: spi@c80000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xc80000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se17_spi_active>;
|
|
pinctrl-1 = <&qupv3_se17_spi_sleep>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se18_spi: spi@c84000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xc84000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se18_spi_active>;
|
|
pinctrl-1 = <&qupv3_se18_spi_sleep>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se19_spi: spi@c88000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xc88000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se19_spi_active>;
|
|
pinctrl-1 = <&qupv3_se19_spi_sleep>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|