mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
169992e806
This change is add settings for change calculation of FoM for preset Change-Id: I64a7be0473ad9fd8f100252df40e986e18a5c756
382 lines
8.1 KiB
Devicetree
382 lines
8.1 KiB
Devicetree
#include "sdxlemur-mtp.dtsi"
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&soc {
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qps615_vreg: qps615_vreg {
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compatible = "regulator-fixed";
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regulator-name = "qps615_vreg";
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gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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enable-active-high;
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regulator-enable-ramp-delay = <4300>;
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};
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qca_vreg: qca_vreg {
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compatible = "regulator-fixed";
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regulator-name = "qca_vreg";
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gpio = <&tlmm 106 GPIO_ACTIVE_HIGH>;
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vin-supply = <&qps615_vreg>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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regulator-enable-ramp-delay = <80000>;
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};
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aqr_vreg: aqr_vreg {
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compatible = "regulator-fixed";
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regulator-name = "aqr_vreg";
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gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>;
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vin-supply = <&qps615_vreg>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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enable-active-high;
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regulator-enable-ramp-delay = <10000>;
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};
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ioss_aqr_rx: qps615_rx@eth0 {
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qcom,dir-rx;
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qcom,rx-filter-ip;
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qcom,ring-size = <1023>;
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qcom,buff-size = <2048>;
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qcom,mod-count-min = <64>;
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qcom,mod-count-max = <64>;
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qcom,mod-usecs-min = <30>;
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qcom,mod-usecs-max = <60>;
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};
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ioss_aqr_tx: qps615_tx@eth0 {
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qcom,dir-tx;
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qcom,ring-size = <1023>;
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qcom,buff-size = <2048>;
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qcom,mod-count-min = <64>;
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qcom,mod-count-max = <64>;
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qcom,mod-usecs-min = <30>;
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qcom,mod-usecs-max = <60>;
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};
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ioss_napa_rx: qps615_rx@eth1 {
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qcom,dir-rx;
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qcom,rx-filter-ip;
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qcom,ring-size = <127>;
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qcom,buff-size = <2048>;
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qcom,mod-count-min = <64>;
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qcom,mod-count-max = <64>;
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qcom,mod-usecs-min = <30>;
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qcom,mod-usecs-max = <60>;
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};
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ioss_napa_tx: qps615_tx@eth1 {
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qcom,dir-tx;
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qcom,ring-size = <511>;
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qcom,buff-size = <2048>;
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qcom,mod-count-min = <64>;
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qcom,mod-count-max = <64>;
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qcom,mod-usecs-min = <30>;
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qcom,mod-usecs-max = <60>;
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};
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};
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&i2c_5 {
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status = "ok"
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pcie_i2c_ctrl: pcie_i2c_ctrl {
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compatible = "qcom,pcie0-i2c-ntn3";
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reg = <0x77>;
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gpio-config-reg = <0x801208>;
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ep-reset-reg = <0x801210>;
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ep-reset-gpio-mask = <0xc>;
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version-reg = <0x800000>;
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dump-regs = <0x801330 0x801350 0x801370>;
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reg_update = <0x82c030 0x1
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0x828000 0x3
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0x82bd00 0x8
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0x82c030 0x2
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0x828000 0x3
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0x82bd00 0x8
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0x82c030 0x8
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0x828000 0x1
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0x82bd00 0x8
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0x82c01c 0x10
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0x82c030 0xf
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0x828000 0xf
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0x82b268 0x2>;
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/*FOM for preset caluclation*/
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switch_reg_update = <0x82c02c 0x00000007
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0x824a10 0x00000001
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0x82c030 0x00000008
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0x828000 0x00000001
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0x82b074 0x00000020
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0x82b2bc 0x00000001>;
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};
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};
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&pcie0 {
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pcie-i2c-phandle = <&i2c_5>;
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vreg-3p3-supply = <&qps615_vreg>;
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qcom,phy-sequence = <0x1240 0x03 0x0
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0x1010 0x01 0x0
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0x101c 0x31 0x0
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0x1020 0x01 0x0
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0x1024 0xde 0x0
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0x1028 0x07 0x0
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0x1030 0x97 0x0
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0x1034 0x0c 0x0
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0x1044 0x14 0x0
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0x1048 0x90 0x0
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0x1058 0x0f 0x0
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0x1074 0x06 0x0
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0x1078 0x06 0x0
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0x107c 0x16 0x0
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0x1080 0x16 0x0
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0x1084 0x36 0x0
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0x1088 0x36 0x0
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0x1094 0x08 0x0
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0x10a4 0x46 0x0
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0x10a8 0x04 0x0
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0x10ac 0x0a 0x0
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0x10b0 0x1a 0x0
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0x10b4 0x14 0x0
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0x10b8 0x34 0x0
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0x10bc 0x82 0x0
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0x10c4 0xd0 0x0
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0x10cc 0x55 0x0
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0x10d0 0x55 0x0
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0x10d4 0x03 0x0
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0x10d8 0x55 0x0
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0x10dc 0x55 0x0
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0x10e0 0x05 0x0
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0x110c 0x02 0x0
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0x1154 0x34 0x0
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0x1158 0x12 0x0
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0x115c 0x00 0x0
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0x1168 0x0a 0x0
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0x116c 0x04 0x0
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0x119c 0x88 0x0
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0x1174 0x60 0x0
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0x117c 0x06 0x0
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0x11a0 0x14 0x0
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0x11a8 0x0f 0x0
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0x0220 0x16 0x0
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0x03c0 0x38 0x0
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0x0a20 0x16 0x0
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0x0bc0 0x38 0x0
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0x0364 0xcc 0x0
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0x0368 0x12 0x0
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0x036c 0xcc 0x0
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0x0374 0x4a 0x0
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0x0378 0x29 0x0
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0x037c 0xc5 0x0
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0x0380 0xac 0x0
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0x0384 0xb6 0x0
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0x0388 0xc0 0x0
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0x038c 0x07 0x0
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0x0390 0xfb 0x0
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0x0394 0x0d 0x0
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0x0398 0xc5 0x0
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0x039c 0xee 0x0
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0x03a0 0xbf 0x0
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0x03a4 0xa0 0x0
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0x03a8 0x81 0x0
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0x03ac 0xde 0x0
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0x03b0 0x7f 0x0
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0x0b64 0xcc 0x0
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0x0b68 0x12 0x0
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0x0b6c 0xcc 0x0
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0x0b74 0x4a 0x0
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0x0b78 0x29 0x0
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0x0b7c 0xc5 0x0
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0x0b80 0xac 0x0
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0x0b84 0xb6 0x0
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0x0b88 0xc0 0x0
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0x0b8c 0x07 0x0
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0x0b90 0xfb 0x0
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0x0b94 0x0d 0x0
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0x0b98 0xc5 0x0
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0x0b9c 0xee 0x0
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0x0ba0 0xbf 0x0
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0x0ba4 0xa0 0x0
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0x0ba8 0x81 0x0
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0x0bac 0xde 0x0
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0x0bb0 0x7f 0x0
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0x03b4 0x20 0x0
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0x022c 0x3f 0x0
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0x0230 0x37 0x0
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0x0bb4 0x20 0x0
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0x0a2c 0x3f 0x0
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0x0a30 0x37 0x0
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0x0078 0x05 0x0
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0x007c 0xf6 0x0
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0x0878 0x05 0x0
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0x087c 0xf6 0x0
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0x0290 0x05 0x0
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0x0a90 0x05 0x0
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0x03f8 0x1f 0x0
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0x0400 0x1f 0x0
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0x0408 0x1f 0x0
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0x0410 0x1f 0x0
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0x0418 0x1f 0x0
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0x0420 0x1f 0x0
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0x03f4 0x1f 0x0
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0x03fc 0x1f 0x0
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0x0404 0x1f 0x0
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0x0bf8 0x1f 0x0
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0x0c00 0x1f 0x0
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0x0c08 0x1f 0x0
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0x0c10 0x1f 0x0
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0x0c18 0x1f 0x0
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0x0c20 0x1f 0x0
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0x0bf4 0x1f 0x0
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0x0bfc 0x1f 0x0
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0x0c04 0x1f 0x0
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0x0208 0x0c 0x0
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0x0a08 0x0c 0x0
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0x020c 0x0a 0x0
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0x0a0c 0x0a 0x0
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0x02dc 0x0a 0x0
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0x0adc 0x0a 0x0
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0x0308 0x0b 0x0
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0x0b08 0x0b 0x0
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0x027c 0x10 0x0
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0x0a7c 0x10 0x0
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0x02b4 0x00 0x0
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0x0ab4 0x00 0x0
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0x02ec 0x0f 0x0
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0x0aec 0x0f 0x0
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0x02c4 0x00 0x0
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0x02c8 0x1f 0x0
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0x0ac4 0x00 0x0
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0x0ac8 0x1f 0x0
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0x0030 0x1a 0x0
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0x0034 0x0c 0x0
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0x0830 0x1a 0x0
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0x0834 0x0c 0x0
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0x141c 0xc1 0x0
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0x1490 0x00 0x0
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0x13e0 0x16 0x0
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0x13e4 0x22 0x0
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0x1508 0x02 0x0
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0x14a0 0x16 0x0
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0x1420 0x40 0x0
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0x1584 0x28 0x0
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0x1370 0x2e 0x0
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0x155c 0x2e 0x0
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0x140c 0x1d 0x0
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0x1388 0xaa 0x0
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0x1200 0x00 0x0
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0x1244 0x03 0x0>;
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iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
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<0x100 &apps_smmu 0x0201 0x1>,
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<0x208 &apps_smmu 0x0202 0x1>,
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<0x210 &apps_smmu 0x0203 0x1>,
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<0x218 &apps_smmu 0x0204 0x1>,
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<0x300 &apps_smmu 0x0207 0x1>,
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<0x400 &apps_smmu 0x0208 0x1>,
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<0x500 &apps_smmu 0x020c 0x1>,
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<0x501 &apps_smmu 0x020e 0x1>;
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};
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&pcie0_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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/* BDF 1.0.0 */
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pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 {
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reg = <0 0 0 0 0>;
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/* BDF 2.1.0 */
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pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 {
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reg = <0x800 0x0 0x0 0x0 0x0>;
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};
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/* BDF 2.2.0 */
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pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 {
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reg = <0x1000 0x0 0x0 0x0 0x0>;
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};
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/* BDF 2.3.0 */
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pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 {
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reg = <0x1800 0x0 0x0 0x0 0x0>;
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qps615_eth0,qps615_eth0@pcie0_rp {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&aqr_intn_wol_sig>;
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compatible = "qcom,ioss-v2-device";
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qcom,phy-rst-gpio = <0>;
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qcom,ioss = <&ioss>;
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qcom,ioss_instance = <0>;
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qcom,ioss_channels =
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<&ioss_aqr_rx>,
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<&ioss_aqr_tx>;
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qcom,ioss-wol-phy;
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interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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/* ipa shares this group */
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qcom,iommu-group = <&ipa_eth_group1>;
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phy-supply = <&aqr_vreg>;
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qcom,phy-rst-delay-us = <221000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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/* BDF 5.0.0 */
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pcie0_bus5_dev0_fn0: pcie0_ntn3_eth0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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qcom,iommu-group = <ð0_pci_iommu_group>;
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eth0_pci_iommu_group: eth0_pci_iommu_group {
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qcom,iommu-dma = "atomic";
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};
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};
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qps615_eth1,qps615_eth1@pcie0_rp {
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reg = <0x100 0x0 0x0 0x0 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&napa_intn_wol_sig>;
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compatible = "qcom,ioss-v2-device";
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qcom,phy-rst-gpio = <1>;
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qcom,ioss = <&ioss>;
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qcom,ioss_instance = <1>;
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qcom,ioss_channels =
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<&ioss_napa_rx>,
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<&ioss_napa_tx>;
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qcom,ioss-wol-phy;
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qcom,ioss-wol-magic;
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interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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/* ipa shares this group */
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qcom,iommu-group = <&ipa_eth_group2>;
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phy-supply = <&qca_vreg>;
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qcom,phy-rst-delay-us = <20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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/* BDF 5.0.1 */
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pcie0_bus5_dev0_fn1: pcie0_ntn3_eth1 {
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reg = <0x100 0x0 0x0 0x0 0x0>;
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qcom,iommu-group = <ð1_pci_iommu_group>;
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eth1_pci_iommu_group: eth1_pci_iommu_group {
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qcom,iommu-dma = "atomic";
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};
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};
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};
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};
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};
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