mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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| Filename | Latest commit message | Latest commit date |
|---|---|---|
9447332ffa
The 35h instruction op code has two aliases/macro definitions: - SPINOR_OP_RDCR from include/linux/mtd/spi-nor.h - SPINOR_OP_RDSR2 from drivers/mtd/devices/serial_flash_cmds.h Actually, some manufacturers name the associated internal register Status Register 2 whereas other manufacturers name it Configuration Register hence the two different macros for the very same instruction op code. Since the spi-nor.h file is the reference file for all SPI NOR instruction op codes, this patch removes the definition of the SPINOR_OP_RDSR2 macro. Also the SPINOR_OP_RDSR2 macro will be associated to another instruction op code in a further patch so we need to avoid a conflict defining this macro twice. Indeed the JESD216 rev B specification, defining the SFDP tables, also refers to the 3Eh and 3Fh instruction op codes to write/read the Status Register 2 on some SPI NOR flash memories, the 35h op code still being used to read the Configuration Register/Status Register 2 on other memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> |
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| .. | ||
| chips | ||
| devices | ||
| lpddr | ||
| maps | ||
| nand | ||
| onenand | ||
| spi-nor | ||
| tests | ||
| ubi | ||
| afs.c | ||
| ar7part.c | ||
| bcm47xxpart.c | ||
| bcm63xxpart.c | ||
| cmdlinepart.c | ||
| ftl.c | ||
| inftlcore.c | ||
| inftlmount.c | ||
| Kconfig | ||
| Makefile | ||
| mtd_blkdevs.c | ||
| mtdblock.c | ||
| mtdblock_ro.c | ||
| mtdchar.c | ||
| mtdconcat.c | ||
| mtdcore.c | ||
| mtdcore.h | ||
| mtdoops.c | ||
| mtdpart.c | ||
| mtdsuper.c | ||
| mtdswap.c | ||
| nftlcore.c | ||
| nftlmount.c | ||
| ofpart.c | ||
| redboot.c | ||
| rfd_ftl.c | ||
| sm_ftl.c | ||
| sm_ftl.h | ||
| ssfdc.c | ||