mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
148ea4b0c5
Replace deprecated PCIe DT entry for PCIe AUX clock controller setting with the correct entry and value. PCIe core controller requires AUX clock to be 16.6MHz for sdxlemur. Change-Id: I2fa8d8c819bfd06f80b2e274f97b282caa90eb70
258 lines
6.2 KiB
Devicetree
258 lines
6.2 KiB
Devicetree
&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x1c00000 0x3000>,
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<0x1c06000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 57 0>;
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wake-gpio = <&tlmm 53 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep
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&pcie0_perst_default
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_gdsc>;
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vreg-1.8-supply = <&pmx65_l1>;
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vreg-0.9-supply = <&pmx65_l4>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>;
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qcom,vreg-0.9-voltage-level = <912000 912000 132000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
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qcom,bw-scale =
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<RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen1 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; /* Gen4 */
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interconnect-names = "icc_path";
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interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
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<&gcc GCC_PCIE_PIPE_CLK_SRC>,
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<&pcie_pipe_clk>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_0_sleep_clk", "pcie_phy_refgen_clk",
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"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>,
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<0>;
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resets = <&gcc GCC_PCIE_BCR>,
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<&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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qcom,smmu-sid-base = <0x0200>;
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iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
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<0x100 &apps_smmu 0x0201 0x1>;
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qcom,aux-clk-freq = <17>; /* 16.6 MHz */
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qcom,slv-addr-space-size = <0x40000000>;
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qcom,ep-latency = <10>;
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qcom,pcie-phy-ver = <1101>;
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qcom,phy-status-offset = <0x1214>;
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qcom,phy-status-bit = <7>;
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qcom,phy-power-down-offset = <0x1240>;
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qcom,phy-sequence = <0x1240 0x03 0x0
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0x1010 0x01 0x0
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0x101c 0x31 0x0
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0x1020 0x01 0x0
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0x1024 0xde 0x0
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0x1028 0x07 0x0
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0x1030 0x97 0x0
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0x1034 0x0c 0x0
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0x1044 0x14 0x0
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0x1048 0x90 0x0
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0x1058 0x0f 0x0
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0x1074 0x06 0x0
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0x1078 0x06 0x0
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0x107c 0x16 0x0
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0x1080 0x16 0x0
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0x1084 0x36 0x0
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0x1088 0x36 0x0
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0x1094 0x08 0x0
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0x10a4 0x46 0x0
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0x10a8 0x04 0x0
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0x10ac 0x0a 0x0
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0x10b0 0x1a 0x0
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0x10b4 0x14 0x0
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0x10b8 0x34 0x0
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0x10bc 0x82 0x0
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0x10c4 0xd0 0x0
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0x10cc 0x55 0x0
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0x10d0 0x55 0x0
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0x10d4 0x03 0x0
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0x10d8 0x55 0x0
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0x10dc 0x55 0x0
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0x10e0 0x05 0x0
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0x110c 0x02 0x0
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0x1154 0x34 0x0
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0x1158 0x12 0x0
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0x115c 0x00 0x0
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0x1168 0x0a 0x0
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0x116c 0x04 0x0
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0x119c 0x88 0x0
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0x1174 0x20 0x0
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0x117c 0x06 0x0
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0x11a0 0x14 0x0
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0x11a8 0x0f 0x0
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0x0220 0x16 0x0
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0x03c0 0x38 0x0
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0x0a20 0x16 0x0
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0x0bc0 0x38 0x0
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0x0364 0xcc 0x0
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0x036c 0xcc 0x0
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0x0378 0x31 0x0
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0x037c 0xc5 0x0
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0x0380 0xcc 0x0
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0x0384 0xb6 0x0
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0x0388 0xc2 0x0
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0x038c 0x17 0x0
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0x0390 0xfb 0x0
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0x0394 0x0f 0x0
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0x039c 0xee 0x0
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0x03a0 0xbf 0x0
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0x03a4 0x80 0x0
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0x03a8 0x81 0x0
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0x03ac 0xdf 0x0
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0x03b0 0x5f 0x0
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0x0b64 0xcc 0x0
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0x0b6c 0xcc 0x0
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0x0b78 0x31 0x0
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0x0b7c 0xc5 0x0
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0x0b80 0xcc 0x0
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0x0b84 0xb6 0x0
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0x0b88 0xc2 0x0
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0x0b8c 0x17 0x0
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0x0b90 0xfb 0x0
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0x0b94 0x0f 0x0
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0x0b9c 0xee 0x0
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0x0ba0 0xbf 0x0
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0x0ba4 0x80 0x0
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0x0ba8 0x81 0x0
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0x0bac 0xdf 0x0
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0x0bb0 0x5f 0x0
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0x03b4 0x20 0x0
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0x022c 0x3f 0x0
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0x0230 0x2d 0x0
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0x0bb4 0x20 0x0
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0x0a2c 0x3f 0x0
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0x0a30 0x2d 0x0
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0x0078 0x05 0x0
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0x007c 0xf6 0x0
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0x0878 0x05 0x0
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0x087c 0xf6 0x0
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0x0290 0x05 0x0
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0x0a90 0x05 0x0
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0x03f8 0x1f 0x0
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0x0400 0x1f 0x0
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0x0408 0x1f 0x0
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0x0410 0x1f 0x0
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0x0418 0x1f 0x0
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0x0420 0x1f 0x0
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0x03f4 0x1f 0x0
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0x03fc 0x1f 0x0
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0x0404 0x1f 0x0
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0x0bf8 0x1f 0x0
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0x0c00 0x1f 0x0
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0x0c08 0x1f 0x0
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0x0c10 0x1f 0x0
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0x0c18 0x1f 0x0
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0x0c20 0x1f 0x0
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0x0bf4 0x1f 0x0
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0x0bfc 0x1f 0x0
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0x0c04 0x1f 0x0
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0x0208 0x0c 0x0
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0x0a08 0x0c 0x0
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0x020c 0x0a 0x0
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0x0a0c 0x0a 0x0
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0x02dc 0x0a 0x0
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0x0adc 0x0a 0x0
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0x0308 0x0b 0x0
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0x0b08 0x0b 0x0
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0x027c 0x1f 0x0
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0x0a7c 0x1f 0x0
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0x02b4 0x00 0x0
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0x0ab4 0x00 0x0
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0x02ec 0x0d 0x0
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0x0aec 0x0d 0x0
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0x02c4 0x00 0x0
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0x02c8 0x1f 0x0
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0x0ac4 0x00 0x0
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0x0ac8 0x1f 0x0
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0x0030 0x1a 0x0
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0x0034 0x0c 0x0
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0x0830 0x1a 0x0
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0x0834 0x0c 0x0
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0x141c 0xc1 0x0
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0x1490 0x00 0x0
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0x13e0 0x16 0x0
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0x13e4 0x22 0x0
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0x1508 0x02 0x0
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0x14a0 0x16 0x0
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0x1584 0x28 0x0
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0x1370 0x2e 0x0
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0x155c 0x2e 0x0
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0x1200 0x00 0x0
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0x1244 0x03 0x0>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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};
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