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Filename Latest commit message Latest commit date
Rakesh Pillai 94ff74fcf9 qcacmn: Add memory barrier to avoid inconsistent reg write
The delayed register write enqueue fills a queue element
with the required data which can be dequeued in a workqueue
running on a different CPU. Since these operations are not
lock protected, there can be stale value access when memory
write has not been flushed to the actual address.

Using write memory barrier before setting the valid flag for
a queue element will make sure that the dequeuing worker
thread will always see the updated values if the element valid
flag is set and thereby avoid any race condition.

Change-Id: I81b0735f0fb39599095ad309157020c691e25a0b
CRs-Fixed: 2665576
2020-04-21 18:48:58 -07:00
cfg
dp qcacmn: Replenish last entry in monitor status ring 2020-04-20 05:54:54 -07:00
ftm
global_lmac_if
hal/wifi3.0 qcacmn: Add memory barrier to avoid inconsistent reg write 2020-04-21 18:48:58 -07:00
hif qcacmn: Add check to avoid panic if FW is down 2020-04-18 13:50:35 -07:00
htc qcacmn: Fix regression issue for EAPOL fail 2020-04-19 01:14:01 -07:00
init_deinit/dispatcher
os_if/linux
qal
qdf qcacmn: Add memory barrier to avoid inconsistent reg write 2020-04-21 18:48:58 -07:00
scheduler
spectral
target_if qcacmn: Trigger recovery before sending failure resp for vdev cmd timeout 2020-04-17 13:20:00 -07:00
umac qcacmn: Add an API wlan_reg_update_pdev_wireless_modes 2020-04-21 14:05:17 -07:00
utils qcacmn: Change qtimer time-stamp from decimal to hex 2020-04-20 10:28:48 -07:00
wbuff
wlan_cfg
wmi qcacmn: Retrieve max tx power allowd from vdev start resp 2020-04-21 01:46:49 -07:00
README.txt
VERSION.txt

 This is CNSS WLAN Host Driver for products starting from iHelium