mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-03 17:27:25 -05:00
30b7ce9288
Added msm poweroff node for all reset functionalities on SA2150P target. Change-Id: I30873323734381c13f1caf5aeb5635f74f5cc9d4
493 lines
10 KiB
Devicetree
493 lines
10 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm Technologies, Inc. QCS405";
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compatible = "qcom,qcs405";
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qcom,msm-id = <352 0x0>, <452 0x0>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &blsp1_uart2_console;
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};
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chosen {
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};
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_mem: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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removed_region0: removed_region@85900000 {
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no-map;
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reg = <0x0 0x85900000 0x0 0x600000>;
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};
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smem_region: smem@85f00000 {
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no-map;
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reg = <0x0 0x85f00000 0x0 0x200000>;
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};
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removed_region1: removed_region@86100000 {
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no-map;
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reg = <0x0 0x86100000 0x0 0x300000>;
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};
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wlan_fw_mem: wlan_fw_mem@86400000 {
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no-map;
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reg = <0x0 0x86400000 0x0 0x1000000>;
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};
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adsp_fw_mem: adsp_fw_mem@87400000 {
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no-map;
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reg = <0x0 0x87400000 0x0 0x1400000>;
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};
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cdsp_fw_mem: cdsp_fw_mem@88800000 {
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no-map;
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reg = <0x0 0x88800000 0x0 0x800000>;
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};
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wlan_msa_mem: wlan_msa_region@88E00000 {
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no-map;
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reg = <0x0 0x89000000 0x0 0x100000>;
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};
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secure_mem: secure_region {
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status = "disabled";
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compatible = "shared-dma-pool";
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x7000000>;
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};
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mdf_mem: mdf_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x800000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x1000000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x400000>;
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x800000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x1000000>;
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linux,cma-default;
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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wakegic: wake-gic {
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compatible = "qcom,mpm-gic-qcs405", "qcom,mpm";
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interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
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reg = <0x601b8 0x1000>,
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<0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
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reg-names = "vmpm", "ipc";
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qcom,num-mpm-irqs = <96>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <2>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb120000 0x1000>;
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clock-frequency = <19200000>;
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frame@b121000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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reg = <0xb121000 0x1000>,
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<0xb122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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reg = <0xb123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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reg = <0xb124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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reg = <0xb125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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reg = <0xb126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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reg = <0xb127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <0 14 0x4>;
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reg = <0xb128000 0x1000>;
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status = "disabled";
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};
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};
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clocks {
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xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>,
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<0x193d100 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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blsp1_uart2_console: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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interrupts = <0 118 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_uart2_default>;
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status = "okay";
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};
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-smd";
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rpm-channel-name = "rpm_requests";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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rpm-channel-type = <15>; /* SMD_APPS_RPM */
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};
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qcom,msm-imem@8600000 {
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compatible = "qcom,msm-imem";
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reg = <0x08600000 0x1000>; /* Address and size of IMEM */
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ranges = <0x0 0x08600000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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dload_type@18 {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x18 0x4>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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};
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tcsr_mutex_block: syscon@1905000 {
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compatible = "syscon";
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reg = <0x1905000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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hwlocks = <&tcsr_mutex 3>;
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};
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apcs: syscon@b011008 {
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compatible = "syscon";
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reg = <0xb011008 0x4>;
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};
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apcs_glb: mailbox@b011000 {
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compatible = "qcom,msm8916-apcs-kpss-global";
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reg = <0xb011000 0x10>;
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#mbox-cells = <1>;
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};
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smp2p_sleepstate: qcom,smp2p_sleepstate {
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compatible = "qcom,smp2p-sleepstate";
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qcom,smem-states = <&sleepstate_smp2p_out 0>;
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};
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rpm_msg_ram: memory@60000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x60000 0x6000>;
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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qcom,rpm_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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qcom,notify-edges = <&glink_adsp>,
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<&glink_cdsp>;
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};
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};
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qcom,glink {
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compatible = "qcom,glink";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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glink_adsp: adsp {
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qcom,remote-pid = <2>;
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transport = "smem";
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mboxes = <&apcs_glb 8>;
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mbox-names = "adsp_smem";
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interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
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label = "adsp";
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qcom,glink-label = "lpass";
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qcom,adsp_qrtr {
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qcom,glink-channels = "IPCRTR";
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qcom,intents = <0x800 5
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0x2000 3
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0x4400 2>;
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};
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qcom,apr_tal_rpmsg {
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qcom,glink-channels = "apr_audio_svc";
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qcom,intents = <0x200 20>;
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};
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qcom,msm_fastrpc_rpmsg {
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compatible = "qcom,msm-fastrpc-rpmsg";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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qcom,intents = <0x64 64>;
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};
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qcom,adsp_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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qcom,notify-edges = <&glink_cdsp>;
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};
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};
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glink_cdsp: cdsp {
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qcom,remote-pid = <5>;
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transport = "smem";
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mboxes = <&apcs_glb 12>;
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mbox-names = "cdsp_smem";
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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label = "cdsp";
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qcom,glink-label = "cdsp";
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qcom,cdsp_qrtr {
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qcom,glink-channels = "IPCRTR";
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qcom,intents = <0x800 5
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0x2000 3
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0x4400 2>;
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};
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qcom,msm_fastrpc_rpmsg {
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compatible = "qcom,msm-fastrpc-rpmsg";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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qcom,intents = <0x64 64>;
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};
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qcom,cdsp_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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qcom,notify-edges = <&glink_adsp>;
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};
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};
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};
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qcom,glinkpkt {
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compatible = "qcom,glinkpkt";
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qcom,glinkpkt-apr-apps2 {
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qcom,glinkpkt-edge = "adsp";
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qcom,glinkpkt-ch-name = "apr_apps2";
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qcom,glinkpkt-dev-name = "apr_apps2";
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};
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};
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qcom,smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 0 10>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sleepstate_smp2p_out: sleepstate-out {
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qcom,entry-name = "sleepstate";
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#qcom,smem-state-cells = <1>;
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};
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};
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qcom,smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 0 14>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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cdsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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cdsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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wdog: qcom,wdt@b017000 {
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compatible = "qcom,msm-watchdog";
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reg = <0xb017000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9744>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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status = "okay";
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};
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};
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#include "qcs405-pinctrl.dtsi"
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#include "qcs405-cpu.dtsi"
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#include "pms405-rpm-regulator.dtsi"
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#include "qcs405-regulator.dtsi"
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#include "qcs405-ion.dtsi"
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