mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 13:44:26 -04:00
921 lines
20 KiB
Devicetree
921 lines
20 KiB
Devicetree
#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
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#include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,dcc_v2.h>
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#include <dt-bindings/sound/qcom,gpr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/interconnect/qcom,sdxlemur.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm Technologies, Inc. SDXLEMUR";
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compatible = "qcom,sdxlemur";
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qcom,msm-id = <458 0x10000>;
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interrupt-parent = <&intc>;
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aliases {
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pci-domain0 = &pcie0; /* PCIe0 domain */
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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reserved_memory: reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00000000 0xffffffff>;
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reusable;
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size = <0x400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00000000 0xffffffff>;
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reusable;
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alignment = <0x400000>;
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size = <0xC00000>;
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linux,cma-default;
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};
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audio_mem: audio_region@0 {
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compatible = "shared-dma-pool";
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no-map;
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size = <0x400000>;
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};
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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enable-method = "psci";
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cpu-idle-states = <&A7_SPC &A7_PC &CX_MIN>;
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};
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};
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soc: soc { };
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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qcom,dload-mode = <&tcsr 0x13000>;
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};
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@17800000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x17800000 0x1000>,
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<0x17802000 0x1000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 12 0xf08>,
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<1 10 0xf08>,
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<1 11 0xf08>;
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clock-frequency = <19200000>;
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};
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timer@17820000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17820000 0x1000>;
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clock-frequency = <19200000>;
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frame@17821000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0x17821000 0x1000>,
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<0x17822000 0x1000>;
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};
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frame@17823000 {
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frame-number = <1>;
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interrupts = <0 8 0x4>;
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reg = <0x17823000 0x1000>;
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status = "disabled";
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};
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frame@17824000 {
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frame-number = <2>;
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interrupts = <0 9 0x4>;
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reg = <0x17824000 0x1000>;
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status = "disabled";
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};
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frame@17825000 {
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frame-number = <3>;
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interrupts = <0 10 0x4>;
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reg = <0x17825000 0x1000>;
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status = "disabled";
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};
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frame@17826000 {
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frame-number = <4>;
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interrupts = <0 11 0x4>;
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reg = <0x17826000 0x1000>;
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status = "disabled";
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};
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frame@17827000 {
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frame-number = <5>;
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interrupts = <0 12 0x4>;
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reg = <0x17827000 0x1000>;
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status = "disabled";
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};
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frame@17828000 {
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frame-number = <6>;
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interrupts = <0 13 0x4>;
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reg = <0x17828000 0x1000>;
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status = "disabled";
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};
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frame@17829000 {
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frame-number = <7>;
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interrupts = <0 14 0x4>;
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reg = <0x17829000 0x1000>;
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status = "disabled";
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};
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};
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restart_pshold: restart@c264000 {
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compatible = "qcom,pshold";
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reg = <0xc264000 0x4>,
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<0x1fd3000 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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dcc: dcc_v2@117f000 {
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compatible = "qcom,dcc-v2";
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reg = <0x117f000 0x1000>,
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<0x1100000 0x2000>;
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qcom,transaction_timeout = <0>;
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reg-names = "dcc-base", "dcc-ram-base";
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dcc-ram-offset = <0x800>;
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};
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wdog: qcom,wdt@17817000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17817000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_PPI 3 IRQ_TYPE_EDGE_RISING>,
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<GIC_PPI 2 IRQ_TYPE_EDGE_RISING>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <10000>;
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qcom,wakeup-enable;
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};
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pil_scm_pas {
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compatible = "qcom,pil-tz-scm-pas";
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interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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qcom,mpm2-sleep-counter@c221000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0xc221000 0x1000>;
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clock-frequency = <32768>;
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};
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mem_dump {
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compatible = "qcom,mem-dump";
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memory-region = <&dump_mem>;
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rpmh {
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qcom,dump-size = <0x200000>;
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qcom,dump-id = <0xec>;
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};
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rpm_sw {
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qcom,dump-size = <0x28000>;
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qcom,dump-id = <0xea>;
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};
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pmic {
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qcom,dump-size = <0x80000>;
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qcom,dump-id = <0xe4>;
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};
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tmc_etf {
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qcom,dump-size = <0x4000>;
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qcom,dump-id = <0xf1>;
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};
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etr_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x100>;
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};
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etf_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x102>;
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};
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misc_data {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xe8>;
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};
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};
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qcom,msm-imem@1468f000 {
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compatible = "qcom,msm-imem";
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reg = <0x1468f000 0x1000>; /* Address and size of IMEM */
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ranges = <0x0 0x1468f000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie_pipe_clk: pcie-0-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_pipe_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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aopcc: clock-controller@0 {
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compatible = "qcom,aop-qmp-clk";
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mboxes = <&qmp_aop 0>;
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mbox-names = "qdss_clk";
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#clock-cells = <1>;
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};
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gcc: clock-controller@0x100000 {
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compatible = "qcom,sdxlemur-gcc", "syscon";
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reg = <0x100000 0x1f7400>;
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reg-name = "cc_base";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
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<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
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"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_apsscc: syscon@17811000 {
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compatible = "syscon";
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reg = <0x17811000 0x20>;
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};
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clock_mccc: syscon@90b0000 {
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compatible = "syscon";
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reg = <0x90b0000 0x54>;
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};
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clock_debugcc: qcom,cc-debug {
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compatible = "qcom,sdxlemur-debugcc";
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qcom,gcc = <&gcc>;
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qcom,apsscc = <&clock_apsscc>;
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qcom,mccc = <&clock_mccc>;
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clock-names = "xo_clk_src";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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#clock-cells = <1>;
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};
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serial_uart: serial@831000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x831000 0x200>;
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interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart3_console_active>;
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pinctrl-1 = <&uart3_console_sleep>;
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status = "ok"
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};
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pil_modem: qcom,mss@4080000 {
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compatible = "qcom,pil-tz-generic";
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reg = <0x4080000 0x100>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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qcom,proxy-clock-names = "xo";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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vdd_mss-supply = <&VDD_MSS_LEVEL>;
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qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
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qcom,firmware-name = "modem";
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memory-region = <&mpss_adsp_mem>;
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qcom,pas-id = <4>;
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qcom,smem-id = <421>;
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qcom,sysmon-id = <0>;
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qcom,ssctl-instance-id = <0x22>;
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interrupts-extended = <&intc 0 250 1>,
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<&modem_smp2p_in 0 0>,
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<&modem_smp2p_in 2 0>,
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<&modem_smp2p_in 1 0>,
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<&modem_smp2p_in 3 0>,
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<&modem_smp2p_in 7 0>;
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interrupt-names = "qcom,wdog",
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"qcom,err-fatal",
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"qcom,proxy-unvote",
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"qcom,err-ready",
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"qcom,stop-ack",
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"qcom,shutdown-ack";
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qcom,smem-states = <&modem_smp2p_out 0>;
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qcom,smem-state-names = "qcom,force-stop";
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status = "ok"
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};
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qnand_1: nand@1b00000 {
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compatible = "qcom,msm-nand";
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reg = <0x01b00000 0x1000>,
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<0x01b04000 0x1c000>;
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reg-names = "nand_phys",
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"bam_phys";
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qcom,reg-adjustment-offset = <0x4000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bam_irq";
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clock-names = "core_clk";
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clocks = <&rpmhcc RPMH_QPIC_CLK>;
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status = "disabled";
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};
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sdhc_1: sdhci@8804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x08804000 0x1000>;
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reg-names = "hc_mem";
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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bus-width = <4>;
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/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
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qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
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qcom,devfreq,freq-table = <50000000 200000000>;
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status = "disabled";
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qos0 {
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mask = <0x1>;
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vote = <44>;
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};
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};
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apsscc: clock-controller@17808100 {
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compatible = "qcom,sdxlemur-apsscc";
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clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>;
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clock-names = "bi_tcxo_ao", "gpll0_out_even";
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reg = <0x17810008 0x16>,
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<0x17808100 0x100>;
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reg-names = "apcs_cmd", "apcs_pll";
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vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
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cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
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qcom,speed0-bin-v0 =
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< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
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< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
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< 1497600000 RPMH_REGULATOR_LEVEL_TURBO>;
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#reset-cells = <1>;
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};
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apps_rsc: rsc@17830000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17830000 0x10000>,
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<0x17840000 0x10000>;
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reg-names = "drv-0", "drv-1";
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <1>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<CONTROL_TCS 1>;
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apps_bcm_voter: bcm_voter {
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compatible = "qcom,bcm-voter";
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};
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system_pm {
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compatible = "qcom,system-pm";
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};
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rpmhcc: clock-controller@1 {
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compatible = "qcom,sdxlemur-rpmh-clk";
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#clock-cells = <1>;
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|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b210000 {
|
|
compatible = "qcom,sdxlemur-pdc";
|
|
reg = <0xb210000 0x10000>;
|
|
qcom,pdc-ranges = <0 147 52>, <52 266 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
/* GCC GDSCs */
|
|
gcc_pcie_gdsc: qcom,gdsc@143004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x143004 0x4>;
|
|
regulator-name = "gcc_pcie_gdsc";
|
|
};
|
|
|
|
gcc_usb30_gdsc: qcom,gdsc@117004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x117004 0x4>;
|
|
regulator-name = "gcc_usb30_gdsc";
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
compatible = "qcom,sdxlemur-system_noc";
|
|
reg = <0x1620000 0x31200>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mem_noc: interconnect@9680000 {
|
|
compatible = "qcom,sdxlemur-mem_noc";
|
|
reg = <0x9680000 0x27200>;
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect {
|
|
compatible = "qcom,sdxlemur-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
cache-controller@9200000 {
|
|
compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
|
|
reg = <0x9200000 0x50000>;
|
|
reg-names = "llcc_base";
|
|
cap-based-alloc-and-pwr-collapse;
|
|
clocks = <&aopcc QDSS_CLK>;
|
|
clock-names = "aopcc_closks";
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
apcs_glb: mailbox@0x17811000 {
|
|
compatible = "qcom,sdxlemur-apcs-gcc";
|
|
reg = <0x17811000 0xb9>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qcom,smp2p-modem@1799000c {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
/* ipa - inbound entry from mss */
|
|
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 15>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,gpr {
|
|
compatible = "qcom,gpr";
|
|
qcom,glink-channels = "modem_apps";
|
|
qcom,intents = <0x200 20>;
|
|
reg = <GPR_DOMAIN_MODEM>;
|
|
|
|
spf_core {
|
|
compatible = "qcom,spf_core";
|
|
reg = <GPR_SVC_ADSP_CORE>;
|
|
};
|
|
|
|
audio-pkt {
|
|
compatible = "qcom,audio-pkt";
|
|
qcom,audiopkt-ch-name = "apr_audio_svc";
|
|
reg = <GPR_SVC_MAX>;
|
|
};
|
|
|
|
audio_prm {
|
|
compatible = "qcom,audio_prm";
|
|
reg = <GPR_SVC_ASM>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-data5-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA5_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl0";
|
|
};
|
|
|
|
qcom,glinkpkt-data6-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA6_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl1";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-data21 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA21";
|
|
qcom,glinkpkt-dev-name = "smd21";
|
|
};
|
|
|
|
qcom,glinkpkt-data22 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA22";
|
|
qcom,glinkpkt-dev-name = "smd22";
|
|
};
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
reg = <0xc310000 0x1000>;
|
|
reg-names = "msgram";
|
|
mboxes = <&apcs_glb 0>;
|
|
interrupts = <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "aop";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aop-msg-client {
|
|
compatible = "qcom,debugfs-qmp-client";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
compatible = "qcom,rmnet-ipa3";
|
|
qcom,rmnet-ipa-ssr;
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
compatible = "qcom,pil-tz-generic";
|
|
qcom,pas-id = <0xf>;
|
|
qcom,firmware-name = "ipa_fws";
|
|
qcom,pil-force-shutdown;
|
|
};
|
|
|
|
ipa_hw: qcom,ipa@03e00000 {
|
|
compatible = "qcom,ipa";
|
|
mboxes = <&qmp_aop 0>;
|
|
reg =
|
|
<0x3e00000 0x84000>,
|
|
<0x3e04000 0xfc000>;
|
|
reg-names = "ipa-base", "gsi-base";
|
|
qcom,ipa-cfg-offset = <0x0140000>;
|
|
interrupts =
|
|
<0 241 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ipa-irq", "gsi-irq";
|
|
qcom,ipa-hw-ver = <21>; /* IPA core version = IPAv5.0 */
|
|
qcom,ipa-hw-mode = <0>;
|
|
qcom,platform-type = <0>; /* MDM platform */
|
|
qcom,ee = <0>;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
qcom,use-xbl-boot;
|
|
qcom,arm-smmu;
|
|
qcom,smmu-fast-map;
|
|
qcom,ipa-wdi3-over-gsi;
|
|
qcom,lan-rx-napi;
|
|
qcom,wan-use-skb-page;
|
|
qcom,tx-wrapper-cache-max-size = <400>;
|
|
qcom,ipa-gpi-event-rp-ddr;
|
|
clock-names = "core_clk";
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
|
qcom,interconnect,num-cases = <5>;
|
|
qcom,interconnect,num-paths = <4>;
|
|
interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>,
|
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
|
<&system_noc MASTER_IPA &system_noc SLAVE_IMEM>,
|
|
<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
|
|
|
|
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa";
|
|
/* No vote */
|
|
qcom,no-vote =
|
|
<0 0 0 0 0 0 0 0>;
|
|
|
|
/* SVS2 */
|
|
qcom,svs2 =
|
|
<150000 600000 150000 1804000 75000 300000 0 76800>;
|
|
|
|
/* SVS */
|
|
qcom,svs =
|
|
<625000 1200000 625000 3072000 312500 700000 0 150000>;
|
|
|
|
/* NOMINAL */
|
|
qcom,nominal =
|
|
<1250000 2400000 1250000 6220800 625000 1500000 0 400000>;
|
|
|
|
/* TURBO */
|
|
qcom,turbo =
|
|
<2000000 3500000 2000000 7219200 1000000 1920000 0 400000>;
|
|
|
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
|
"TURBO";
|
|
qcom,throughput-threshold = <600 2500 5000>;
|
|
qcom,scaling-exceptions = <>;
|
|
|
|
ipa_smmu_ap: ipa_smmu_ap {
|
|
compatible = "qcom,ipa-smmu-ap-cb";
|
|
iommus = <&apps_smmu 0x5E0 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
qcom,additional-mapping =
|
|
/* modem tables in IMEM */
|
|
<0x14688000 0x14688000 0x3000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,ipa-q6-smem-size = <36864>;
|
|
};
|
|
|
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
|
iommus = <&apps_smmu 0x5E1 0x0>;
|
|
qcom,iommu-dma = "atomic";
|
|
};
|
|
|
|
ipa_smmu_uc: ipa_smmu_uc {
|
|
compatible = "qcom,ipa-smmu-uc-cb";
|
|
iommus = <&apps_smmu 0x5E2 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
qcom,iommu-dma = "atomic";
|
|
};
|
|
|
|
ipa_smmu_11ad: ipa_smmu_11ad {
|
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
|
iommus = <&apps_smmu 0x5E3 0x0>;
|
|
qcom,shared-cb;
|
|
qcom,iommu-group = <>;
|
|
};
|
|
|
|
/* smp2p information */
|
|
qcom,smp2p_map_ipa_1_out {
|
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
|
qcom,smem-states = <&smp2p_ipa_1_out 0>;
|
|
qcom,smem-state-names = "ipa-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_map_ipa_1_in {
|
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
|
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
|
|
interrupt-names = "ipa-smp2p-in";
|
|
};
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0xd00>,
|
|
<0xc600000 0x2000000>,
|
|
<0xe600000 0x100000>,
|
|
<0xe700000 0xa0000>,
|
|
<0xc40a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x400000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
qcom,vm-nav-path;
|
|
};
|
|
};
|
|
|
|
#include "sdxlemur-pinctrl.dtsi"
|
|
#include "sdxlemur-regulators.dtsi"
|
|
#include "msm-arm-smmu-sdxlemur.dtsi"
|
|
#include "sdxlemur-ion.dtsi"
|
|
#include "sdxlemur-usb.dtsi"
|
|
#include "sdxlemur-pm.dtsi"
|
|
#include "sdxlemur-pcie.dtsi"
|
|
#include "sdxlemur-blsp.dtsi"
|
|
#include "sdxlemur-audio.dtsi"
|
|
#include "sdxlemur-thermal.dtsi"
|