A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-24 21:54:34 -04:00
Code Issues Projects Releases Packages Wiki Activity
android_kernel_motorola_sm6375/qcom/lahaina.dtsi
Christopher Braga 229a222ec9 ARM: dts: msm: Introduce demura HFC region nodes 
ABL expects the demura HFC region nodes to always be present
under a device's reserved memory regions. If this node is not
present, ABL is unable to insert it and demura continuous
splash cannot be handled.

Introduce dummy demura HFC regions into the device tree.
These nodes are given an address and size of 0 to allow the
kernel to specially handle them.

Change-Id: I6b95a145b4d515e24a454d9ad293e477e6dec66f
2021-01-05 11:46:39 -05:00

5774 lines
147 KiB
Devicetree
Raw Blame History

#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-lahaina.h>
#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
#include <dt-bindings/clock/qcom,gcc-lahaina.h>
#include <dt-bindings/clock/qcom,gpucc-lahaina.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-lahaina.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,epss-l3.h>
#include <dt-bindings/interconnect/qcom,lahaina.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/gpio/gpio.h>
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
opp-supported-hw = <ddrtype>;}
#define DDR_TYPE_LPDDR4X 7
#define DDR_TYPE_LPDDR5 8
/ {
model = "Qualcomm Technologies, Inc. Lahaina";
compatible = "qcom,lahaina";
qcom,msm-id = <415 0x10000>, <456 0x10000>, <501 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
mboxes = <&qmp_aop 0>;
};
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
sdhc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &qupv3_se3_2uart;
hsuart0 = &qupv3_se18_4uart;
pci-domain0 = &pcie0; /* PCIe0 domain */
pci-domain1 = &pcie1; /* PCIe1 domain */
swr0 = &swr0;
swr1 = &swr1;
swr2 = &swr2;
usb0 = &usb0;
usb1 = &usb1;
};
firmware: firmware {};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
capacity-dmips-mhz = <2048>;
dynamic-power-coefficient = <845>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
};
cluster2 {
core0 {
cpu = <&CPU7>;
};
};
};
};
soc: soc { };
};
&firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
};
};
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_region@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: reserved-memory@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
cdsp_secure_heap: cdsp_secure_heap@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0x4600000>;
};
pil_camera_mem: pil_camera_region@85200000 {
no-map;
reg = <0x0 0x85200000 0x0 0x500000>;
};
pil_video_mem: pil_video_region@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x500000>;
};
pil_cvp_mem: pil_cvp_region@85c00000 {
no-map;
reg = <0x0 0x85c00000 0x0 0x500000>;
};
pil_adsp_mem: pil_adsp_region@86100000 {
no-map;
reg = <0x0 0x86100000 0x0 0x2100000>;
};
pil_slpi_mem: pil_slpi_region@88200000 {
no-map;
reg = <0x0 0x88200000 0x0 0x1500000>;
};
pil_cdsp_mem: pil_cdsp_region@89700000 {
no-map;
reg = <0x0 0x89700000 0x0 0x1e00000>;
};
pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 {
no-map;
reg = <0x0 0x8b500000 0x0 0x10000>;
};
pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 {
no-map;
reg = <0x0 0x8b510000 0x0 0xa000>;
};
pil_gpu_mem: pil_gpu_region@8b51a000 {
no-map;
reg = <0x0 0x8b51a000 0x0 0x2000>;
};
pil_spss_mem: pil_spss_region@8b600000 {
no-map;
reg = <0x0 0x8b600000 0x0 0x100000>;
};
pil_modem_mem: modem_region@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0x10000000>;
};
hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 {
no-map;
reg = <0x0 0xd0000000 0x0 0x800000>;
};
pil_trustedvm_mem: pil_trustedvm_region@d0800000 {
no-map;
reg = <0x0 0xd0800000 0x0 0x76f7000>;
};
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
chan0_shbuf: neuron_block@0 {
no-map;
reg = <0x0 0xd7f00000 0x0 0x80000>;
};
chan1_shbuf: neuron_block@1 {
no-map;
reg = <0x0 0xd7f80000 0x0 0x80000>;
};
removed_mem: removed_region@d8800000 {
no-map;
reg = <0x0 0xd8800000 0x0 0x6800000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
sdsp_mem: sdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region { /* Secure UI */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xA400000>;
};
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x3000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
audio_cma_mem: audio_cma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1C00000>;
};
splash_memory:splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
/*
* Demura memory regions are to be commented out if
* feature not in use.
*/
demura_memory_0: demura_region_0 {
reg = <0x0 0x0 0x0 0x0>;
label = "demura hfc region 0";
};
demura_memory_1: demura_region_1 {
reg = <0x0 0x0 0x0 0x0>;
label = "demura hfc region 1";
};
dfps_data_memory: dfps_data_region {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_region";
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
/*
* Memory shared with modem needs to be outside of
* the CLADE address space, which begins at
* 0xE0000000 and spans 512 MB.
*/
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
system_pm {
compatible = "qcom,system-pm";
};
clock_rpmh: qcom,rpmhclk {
compatible = "qcom,lahaina-rpmh-clk";
#clock-cells = <1>;
};
};
slim_aud: slim@3ac0000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0x3ac0000 0x2c000>,
<0x3a84000 0x22000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x350>;
iommus = <&apps_smmu 0x1826 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
/* Slimbus Slave DT for QCA6490 */
btfmslim_codec: qca6490 {
compatible = "qcom,btfmslim_slave";
elemental-addr = [00 01 21 02 17 02];
qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
qcom,btfm-slim-ifd-elemental-addr = [00 00 21 02 17 02];
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1112000 0x6000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
link_list1 {
qcom,curr-link-list = <6>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_WRITE 0x18080010 0x1 0>,
<DCC_READ 0x00144018 1 0>,
<DCC_WRITE 0x00144018 0x1 0>,
<DCC_READ 0x00144018 1 0>,
<DCC_READ 0x091a9020 1 0>,
<DCC_READ_WRITE 0x5 0x1 0>,
<DCC_READ 0x09102008 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09142008 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09102408 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09142408 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09103808 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x09103810 1 0>,
<DCC_READ 0x09103814 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09103888 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x09103890 1 0>,
<DCC_READ 0x09103894 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143808 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x09143810 1 0>,
<DCC_READ 0x09143814 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143888 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x09143890 1 0>,
<DCC_READ 0x09143894 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182808 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x09182810 1 0>,
<DCC_READ 0x09182814 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182888 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x09182890 1 0>,
<DCC_READ 0x09182894 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09103008 1 0>,
<DCC_READ 0x0910300c 1 0>,
<DCC_WRITE 0x09103028 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09103010 1 0>,
<DCC_READ 0x09103014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09103408 1 0>,
<DCC_READ 0x0910340c 1 0>,
<DCC_WRITE 0x09103428 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09103410 1 0>,
<DCC_READ 0x09103414 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143008 1 0>,
<DCC_READ 0x0914300c 1 0>,
<DCC_WRITE 0x09143028 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09143010 1 0>,
<DCC_READ 0x09143014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143408 1 0>,
<DCC_READ 0x0914340c 1 0>,
<DCC_WRITE 0x09143428 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09143410 1 0>,
<DCC_READ 0x09143414 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182008 1 0>,
<DCC_READ 0x0918200c 1 0>,
<DCC_WRITE 0x09182028 0x00000001 1>,
<DCC_LOOP 11 0 0>,
<DCC_READ 0x09182010 1 0>,
<DCC_READ 0x09182014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182408 1 0>,
<DCC_READ 0x0918240c 1 0>,
<DCC_WRITE 0x09182428 0x00000001 1>,
<DCC_LOOP 11 0 0>,
<DCC_READ 0x09182410 1 0>,
<DCC_READ 0x09182414 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x18000024 1 0>,
<DCC_READ 0x18000040 4 0>,
<DCC_READ 0x18010024 1 0>,
<DCC_READ 0x18010040 4 0>,
<DCC_READ 0x18020024 1 0>,
<DCC_READ 0x18020040 4 0>,
<DCC_READ 0x18030024 1 0>,
<DCC_READ 0x18030040 4 0>,
<DCC_READ 0x18040024 1 0>,
<DCC_READ 0x18040040 4 0>,
<DCC_READ 0x18050024 1 0>,
<DCC_READ 0x18050040 4 0>,
<DCC_READ 0x18060024 1 0>,
<DCC_READ 0x18060040 4 0>,
<DCC_READ 0x18070024 1 0>,
<DCC_READ 0x18070040 4 0>,
<DCC_READ 0x18080024 1 0>,
<DCC_READ 0x18080040 3 0>,
<DCC_READ 0x180800f8 1 0>,
<DCC_READ 0x18080104 1 0>,
<DCC_READ 0x1808011c 1 0>,
<DCC_READ 0x18080128 1 0>,
<DCC_READ 0x18080168 1 0>,
<DCC_READ 0x18080198 1 0>,
<DCC_READ 0x9050078 1 0>,
<DCC_READ 0x9050110 8 0>,
<DCC_READ 0x9080058 2 0>,
<DCC_READ 0x90800c8 1 0>,
<DCC_READ 0x90800d4 1 0>,
<DCC_READ 0x90800e0 1 0>,
<DCC_READ 0x90800ec 1 0>,
<DCC_READ 0x90800f8 1 0>,
<DCC_READ 0x9084030 1 0>,
<DCC_READ 0x9084038 2 0>,
<DCC_READ 0x90840e4 1 0>,
<DCC_READ 0x90840f4 1 0>,
<DCC_READ 0x9084104 2 0>,
<DCC_READ 0x9084194 1 0>,
<DCC_READ 0x9084804 1 0>,
<DCC_READ 0x908480c 1 0>,
<DCC_READ 0x9084844 1 0>,
<DCC_READ 0x9084850 2 0>,
<DCC_READ 0x9084860 3 0>,
<DCC_READ 0x9084888 1 0>,
<DCC_READ 0x908488c 1 0>,
<DCC_READ 0x9084900 1 0>,
<DCC_READ 0x908409c 1 0>,
<DCC_READ 0x90840a0 1 0>,
<DCC_READ 0x908426c 1 0>,
<DCC_READ 0x908439c 1 0>,
<DCC_READ 0x9085124 1 0>,
<DCC_READ 0x90ba280 1 0>,
<DCC_READ 0x90ba288 7 0>,
<DCC_READ 0x9258610 4 0>,
<DCC_READ 0x92d8610 4 0>,
<DCC_READ 0x9358610 4 0>,
<DCC_READ 0x93d8610 4 0>,
<DCC_READ 0x9220344 8 0>,
<DCC_READ 0x9220370 6 0>,
<DCC_READ 0x9220480 1 0>,
<DCC_READ 0x9222400 1 0>,
<DCC_READ 0x922240c 1 0>,
<DCC_READ 0x9223214 2 0>,
<DCC_READ 0x9223220 3 0>,
<DCC_READ 0x9223308 1 0>,
<DCC_READ 0x9223318 1 0>,
<DCC_READ 0x9232100 1 0>,
<DCC_READ 0x9236040 6 0>,
<DCC_READ 0x92360b0 1 0>,
<DCC_READ 0x923a004 4 0>,
<DCC_READ 0x923e030 2 0>,
<DCC_READ 0x9241000 1 0>,
<DCC_READ 0x9242028 1 0>,
<DCC_READ 0x9242044 3 0>,
<DCC_READ 0x9242070 1 0>,
<DCC_READ 0x9248030 1 0>,
<DCC_READ 0x9248048 8 0>,
<DCC_READ 0x92a0344 8 0>,
<DCC_READ 0x92a0370 6 0>,
<DCC_READ 0x92a0480 1 0>,
<DCC_READ 0x92a2400 1 0>,
<DCC_READ 0x92a240c 1 0>,
<DCC_READ 0x92a3214 2 0>,
<DCC_READ 0x92a3220 3 0>,
<DCC_READ 0x92a3308 1 0>,
<DCC_READ 0x92a3318 1 0>,
<DCC_READ 0x92b2100 1 0>,
<DCC_READ 0x92b6040 6 0>,
<DCC_READ 0x92b60b0 1 0>,
<DCC_READ 0x92ba004 4 0>,
<DCC_READ 0x92be030 2 0>,
<DCC_READ 0x92c1000 1 0>,
<DCC_READ 0x92c2028 1 0>,
<DCC_READ 0x92c2044 3 0>,
<DCC_READ 0x92c2070 1 0>,
<DCC_READ 0x92c8030 1 0>,
<DCC_READ 0x92c8048 8 0>,
<DCC_READ 0x9320344 8 0>,
<DCC_READ 0x9320370 6 0>,
<DCC_READ 0x9320480 1 0>,
<DCC_READ 0x9322400 1 0>,
<DCC_READ 0x932240c 1 0>,
<DCC_READ 0x9323214 2 0>,
<DCC_READ 0x9323220 3 0>,
<DCC_READ 0x9323308 1 0>,
<DCC_READ 0x9323318 1 0>,
<DCC_READ 0x9332100 1 0>,
<DCC_READ 0x9336040 6 0>,
<DCC_READ 0x93360b0 1 0>,
<DCC_READ 0x933a004 4 0>,
<DCC_READ 0x933e030 2 0>,
<DCC_READ 0x9341000 1 0>,
<DCC_READ 0x9342028 1 0>,
<DCC_READ 0x9342044 3 0>,
<DCC_READ 0x9342070 1 0>,
<DCC_READ 0x9348030 1 0>,
<DCC_READ 0x9348048 8 0>,
<DCC_READ 0x93a0344 8 0>,
<DCC_READ 0x93a0370 6 0>,
<DCC_READ 0x93a0480 1 0>,
<DCC_READ 0x93a2400 1 0>,
<DCC_READ 0x93a240c 1 0>,
<DCC_READ 0x93a3214 2 0>,
<DCC_READ 0x93a3220 3 0>,
<DCC_READ 0x93a3308 1 0>,
<DCC_READ 0x93a3318 1 0>,
<DCC_READ 0x93b2100 1 0>,
<DCC_READ 0x93b6040 6 0>,
<DCC_READ 0x93b60b0 1 0>,
<DCC_READ 0x93ba004 4 0>,
<DCC_READ 0x93be030 2 0>,
<DCC_READ 0x93c1000 1 0>,
<DCC_READ 0x93c2028 1 0>,
<DCC_READ 0x93c2044 3 0>,
<DCC_READ 0x93c2070 1 0>,
<DCC_READ 0x93c8030 1 0>,
<DCC_READ 0x93c8048 8 0>,
<DCC_READ 0x9270080 1 0>,
<DCC_READ 0x9270310 1 0>,
<DCC_READ 0x9270400 1 0>,
<DCC_READ 0x9270410 6 0>,
<DCC_READ 0x9270430 1 0>,
<DCC_READ 0x9270440 1 0>,
<DCC_READ 0x9270448 1 0>,
<DCC_READ 0x92704a0 1 0>,
<DCC_READ 0x92704b0 1 0>,
<DCC_READ 0x92704b8 2 0>,
<DCC_READ 0x92704d0 2 0>,
<DCC_READ 0x9271400 1 0>,
<DCC_READ 0x9271408 1 0>,
<DCC_READ 0x927341c 1 0>,
<DCC_READ 0x92753b0 1 0>,
<DCC_READ 0x9275804 1 0>,
<DCC_READ 0x9275c1c 1 0>,
<DCC_READ 0x9275c2c 1 0>,
<DCC_READ 0x9275c38 1 0>,
<DCC_READ 0x9276418 2 0>,
<DCC_READ 0x9279100 1 0>,
<DCC_READ 0x9279110 1 0>,
<DCC_READ 0x9279120 1 0>,
<DCC_READ 0x9279180 2 0>,
<DCC_READ 0x92f0080 1 0>,
<DCC_READ 0x92f0310 1 0>,
<DCC_READ 0x92f0400 1 0>,
<DCC_READ 0x92f0410 6 0>,
<DCC_READ 0x92f0430 1 0>,
<DCC_READ 0x92f0440 1 0>,
<DCC_READ 0x92f0448 1 0>,
<DCC_READ 0x92f04a0 1 0>,
<DCC_READ 0x92f04b0 1 0>,
<DCC_READ 0x92f04b8 2 0>,
<DCC_READ 0x92f04d0 2 0>,
<DCC_READ 0x92f1400 1 0>,
<DCC_READ 0x92f1408 1 0>,
<DCC_READ 0x92f341c 1 0>,
<DCC_READ 0x92f53b0 1 0>,
<DCC_READ 0x92f5804 1 0>,
<DCC_READ 0x92f5c1c 1 0>,
<DCC_READ 0x92f5c2c 1 0>,
<DCC_READ 0x92f5c38 1 0>,
<DCC_READ 0x92f6418 2 0>,
<DCC_READ 0x92f9100 1 0>,
<DCC_READ 0x92f9110 1 0>,
<DCC_READ 0x92f9120 1 0>,
<DCC_READ 0x92f9180 2 0>,
<DCC_READ 0x9370080 1 0>,
<DCC_READ 0x9370310 1 0>,
<DCC_READ 0x9370400 1 0>,
<DCC_READ 0x9370410 6 0>,
<DCC_READ 0x9370430 1 0>,
<DCC_READ 0x9370440 1 0>,
<DCC_READ 0x9370448 1 0>,
<DCC_READ 0x93704a0 1 0>,
<DCC_READ 0x93704b0 1 0>,
<DCC_READ 0x93704b8 2 0>,
<DCC_READ 0x93704d0 2 0>,
<DCC_READ 0x9371400 1 0>,
<DCC_READ 0x9371408 1 0>,
<DCC_READ 0x937341c 1 0>,
<DCC_READ 0x93753b0 1 0>,
<DCC_READ 0x9375804 1 0>,
<DCC_READ 0x9375c1c 1 0>,
<DCC_READ 0x9375c2c 1 0>,
<DCC_READ 0x9375c38 1 0>,
<DCC_READ 0x9376418 2 0>,
<DCC_READ 0x9379100 1 0>,
<DCC_READ 0x9379110 1 0>,
<DCC_READ 0x9379120 1 0>,
<DCC_READ 0x9379180 2 0>,
<DCC_READ 0x93f0080 1 0>,
<DCC_READ 0x93f0310 1 0>,
<DCC_READ 0x93f0400 1 0>,
<DCC_READ 0x93f0410 6 0>,
<DCC_READ 0x93f0430 1 0>,
<DCC_READ 0x93f0440 1 0>,
<DCC_READ 0x93f0448 1 0>,
<DCC_READ 0x93f04a0 1 0>,
<DCC_READ 0x93f04b0 1 0>,
<DCC_READ 0x93f04b8 2 0>,
<DCC_READ 0x93f04d0 2 0>,
<DCC_READ 0x93f1400 1 0>,
<DCC_READ 0x93f1408 1 0>,
<DCC_READ 0x93f341c 1 0>,
<DCC_READ 0x93f53b0 1 0>,
<DCC_READ 0x93f5804 1 0>,
<DCC_READ 0x93f5c1c 1 0>,
<DCC_READ 0x93f5c2c 1 0>,
<DCC_READ 0x93f5c38 1 0>,
<DCC_READ 0x93f6418 2 0>,
<DCC_READ 0x93f9100 1 0>,
<DCC_READ 0x93f9110 1 0>,
<DCC_READ 0x93f9120 1 0>,
<DCC_READ 0x93f9180 2 0>,
<DCC_READ 0x9260080 1 0>,
<DCC_READ 0x9260400 1 0>,
<DCC_READ 0x9260410 3 0>,
<DCC_READ 0x9260420 2 0>,
<DCC_READ 0x9260430 1 0>,
<DCC_READ 0x9260440 1 0>,
<DCC_READ 0x9260448 1 0>,
<DCC_READ 0x92604a0 1 0>,
<DCC_READ 0x92604b0 1 0>,
<DCC_READ 0x92604b8 2 0>,
<DCC_READ 0x92604d0 2 0>,
<DCC_READ 0x9261400 1 0>,
<DCC_READ 0x9263410 1 0>,
<DCC_READ 0x92653b0 1 0>,
<DCC_READ 0x9265804 1 0>,
<DCC_READ 0x9265b1c 1 0>,
<DCC_READ 0x9265b2c 1 0>,
<DCC_READ 0x9265b38 1 0>,
<DCC_READ 0x9269100 1 0>,
<DCC_READ 0x9269108 1 0>,
<DCC_READ 0x9269110 1 0>,
<DCC_READ 0x9269118 1 0>,
<DCC_READ 0x9269120 1 0>,
<DCC_READ 0x9269180 2 0>,
<DCC_READ 0x92e0080 1 0>,
<DCC_READ 0x92e0400 1 0>,
<DCC_READ 0x92e0410 3 0>,
<DCC_READ 0x92e0420 2 0>,
<DCC_READ 0x92e0430 1 0>,
<DCC_READ 0x92e0440 1 0>,
<DCC_READ 0x92e0448 1 0>,
<DCC_READ 0x92e04a0 1 0>,
<DCC_READ 0x92e04b0 1 0>,
<DCC_READ 0x92e04b8 2 0>,
<DCC_READ 0x92e04d0 2 0>,
<DCC_READ 0x92e1400 1 0>,
<DCC_READ 0x92e3410 1 0>,
<DCC_READ 0x92e53b0 1 0>,
<DCC_READ 0x92e5804 1 0>,
<DCC_READ 0x92e5b1c 1 0>,
<DCC_READ 0x92e5b2c 1 0>,
<DCC_READ 0x92e5b38 1 0>,
<DCC_READ 0x92e9100 1 0>,
<DCC_READ 0x92e9108 1 0>,
<DCC_READ 0x92e9110 1 0>,
<DCC_READ 0x92e9118 1 0>,
<DCC_READ 0x92e9120 1 0>,
<DCC_READ 0x92e9180 2 0>,
<DCC_READ 0x9360080 1 0>,
<DCC_READ 0x9360400 1 0>,
<DCC_READ 0x9360410 3 0>,
<DCC_READ 0x9360420 2 0>,
<DCC_READ 0x9360430 1 0>,
<DCC_READ 0x9360440 1 0>,
<DCC_READ 0x9360448 1 0>,
<DCC_READ 0x93604a0 1 0>,
<DCC_READ 0x93604b0 1 0>,
<DCC_READ 0x93604b8 2 0>,
<DCC_READ 0x93604d0 2 0>,
<DCC_READ 0x9361400 1 0>,
<DCC_READ 0x9363410 1 0>,
<DCC_READ 0x93653b0 1 0>,
<DCC_READ 0x9365804 1 0>,
<DCC_READ 0x9365b1c 1 0>,
<DCC_READ 0x9365b2c 1 0>,
<DCC_READ 0x9365b38 1 0>,
<DCC_READ 0x9369100 1 0>,
<DCC_READ 0x9369108 1 0>,
<DCC_READ 0x9369110 1 0>,
<DCC_READ 0x9369118 1 0>,
<DCC_READ 0x9369120 1 0>,
<DCC_READ 0x9369180 2 0>,
<DCC_READ 0x93e0080 1 0>,
<DCC_READ 0x93e0400 1 0>,
<DCC_READ 0x93e0410 3 0>,
<DCC_READ 0x93e0420 2 0>,
<DCC_READ 0x93e0430 1 0>,
<DCC_READ 0x93e0440 1 0>,
<DCC_READ 0x93e0448 1 0>,
<DCC_READ 0x93e04a0 1 0>,
<DCC_READ 0x93e04b0 1 0>,
<DCC_READ 0x93e04b8 2 0>,
<DCC_READ 0x93e04d0 2 0>,
<DCC_READ 0x93e1400 1 0>,
<DCC_READ 0x93e3410 1 0>,
<DCC_READ 0x93e53b0 1 0>,
<DCC_READ 0x93e5804 1 0>,
<DCC_READ 0x93e5b1c 1 0>,
<DCC_READ 0x93e5b2c 1 0>,
<DCC_READ 0x93e5b38 1 0>,
<DCC_READ 0x93e9100 1 0>,
<DCC_READ 0x93e9108 1 0>,
<DCC_READ 0x93e9110 1 0>,
<DCC_READ 0x93e9118 1 0>,
<DCC_READ 0x93e9120 1 0>,
<DCC_READ 0x93e9180 2 0>,
<DCC_READ 0x96b0868 1 0>,
<DCC_READ 0x96b0870 1 0>,
<DCC_READ 0x96b1004 1 0>,
<DCC_READ 0x96b100c 1 0>,
<DCC_READ 0x96b1014 1 0>,
<DCC_READ 0x96b1204 1 0>,
<DCC_READ 0x96b120c 1 0>,
<DCC_READ 0x96b1214 1 0>,
<DCC_READ 0x96b1504 1 0>,
<DCC_READ 0x96b150c 1 0>,
<DCC_READ 0x96b1514 1 0>,
<DCC_READ 0x96b1604 1 0>,
<DCC_READ 0x96b8100 1 0>,
<DCC_READ 0x96b813c 1 0>,
<DCC_READ 0x96b8500 1 0>,
<DCC_READ 0x96b853c 1 0>,
<DCC_READ 0x96b8a04 1 0>,
<DCC_READ 0x96b8a18 1 0>,
<DCC_READ 0x96b8ea8 1 0>,
<DCC_READ 0x96b9044 1 0>,
<DCC_READ 0x96b904c 1 0>,
<DCC_READ 0x96b9054 1 0>,
<DCC_READ 0x96b905c 1 0>,
<DCC_READ 0x96b910c 2 0>,
<DCC_READ 0x96b9204 1 0>,
<DCC_READ 0x96b920c 1 0>,
<DCC_READ 0x96b9238 1 0>,
<DCC_READ 0x96b9240 1 0>,
<DCC_READ 0x96b926c 1 0>,
<DCC_READ 0x96b9394 1 0>,
<DCC_READ 0x96b939c 1 0>,
<DCC_READ 0x96b9704 1 0>,
<DCC_READ 0x96b970c 1 0>,
<DCC_READ 0x96f0868 1 0>,
<DCC_READ 0x96f0870 1 0>,
<DCC_READ 0x96f1004 1 0>,
<DCC_READ 0x96f100c 1 0>,
<DCC_READ 0x96f1014 1 0>,
<DCC_READ 0x96f1204 1 0>,
<DCC_READ 0x96f120c 1 0>,
<DCC_READ 0x96f1214 1 0>,
<DCC_READ 0x96f1504 1 0>,
<DCC_READ 0x96f150c 1 0>,
<DCC_READ 0x96f1514 1 0>,
<DCC_READ 0x96f1604 1 0>,
<DCC_READ 0x96f8100 1 0>,
<DCC_READ 0x96f813c 1 0>,
<DCC_READ 0x96f8500 1 0>,
<DCC_READ 0x96f853c 1 0>,
<DCC_READ 0x96f8a04 1 0>,
<DCC_READ 0x96f8a18 1 0>,
<DCC_READ 0x96f8ea8 1 0>,
<DCC_READ 0x96f9044 1 0>,
<DCC_READ 0x96f904c 1 0>,
<DCC_READ 0x96f9054 1 0>,
<DCC_READ 0x96f905c 1 0>,
<DCC_READ 0x96f910c 2 0>,
<DCC_READ 0x96f9204 1 0>,
<DCC_READ 0x96f920c 1 0>,
<DCC_READ 0x96f9238 1 0>,
<DCC_READ 0x96f9240 1 0>,
<DCC_READ 0x96f926c 1 0>,
<DCC_READ 0x96f9394 1 0>,
<DCC_READ 0x96f939c 1 0>,
<DCC_READ 0x96f9704 1 0>,
<DCC_READ 0x96f970c 1 0>,
<DCC_READ 0x9730868 1 0>,
<DCC_READ 0x9730870 1 0>,
<DCC_READ 0x9731004 1 0>,
<DCC_READ 0x973100c 1 0>,
<DCC_READ 0x9731014 1 0>,
<DCC_READ 0x9731204 1 0>,
<DCC_READ 0x973120c 1 0>,
<DCC_READ 0x9731214 1 0>,
<DCC_READ 0x9731504 1 0>,
<DCC_READ 0x973150c 1 0>,
<DCC_READ 0x9731514 1 0>,
<DCC_READ 0x9731604 1 0>,
<DCC_READ 0x9738100 1 0>,
<DCC_READ 0x973813c 1 0>,
<DCC_READ 0x9738500 1 0>,
<DCC_READ 0x973853c 1 0>,
<DCC_READ 0x9738a04 1 0>,
<DCC_READ 0x9738a18 1 0>,
<DCC_READ 0x9738ea8 1 0>,
<DCC_READ 0x9739044 1 0>,
<DCC_READ 0x973904c 1 0>,
<DCC_READ 0x9739054 1 0>,
<DCC_READ 0x973905c 1 0>,
<DCC_READ 0x973910c 2 0>,
<DCC_READ 0x9739204 1 0>,
<DCC_READ 0x973920c 1 0>,
<DCC_READ 0x9739238 1 0>,
<DCC_READ 0x9739240 1 0>,
<DCC_READ 0x973926c 1 0>,
<DCC_READ 0x9739394 1 0>,
<DCC_READ 0x973939c 1 0>,
<DCC_READ 0x9739704 1 0>,
<DCC_READ 0x973970c 1 0>,
<DCC_READ 0x9770868 1 0>,
<DCC_READ 0x9770870 1 0>,
<DCC_READ 0x9771004 1 0>,
<DCC_READ 0x977100c 1 0>,
<DCC_READ 0x9771014 1 0>,
<DCC_READ 0x9771204 1 0>,
<DCC_READ 0x977120c 1 0>,
<DCC_READ 0x9771214 1 0>,
<DCC_READ 0x9771504 1 0>,
<DCC_READ 0x977150c 1 0>,
<DCC_READ 0x9771514 1 0>,
<DCC_READ 0x9771604 1 0>,
<DCC_READ 0x9778100 1 0>,
<DCC_READ 0x977813c 1 0>,
<DCC_READ 0x9778500 1 0>,
<DCC_READ 0x977853c 1 0>,
<DCC_READ 0x9778a04 1 0>,
<DCC_READ 0x9778a18 1 0>,
<DCC_READ 0x9778ea8 1 0>,
<DCC_READ 0x9779044 1 0>,
<DCC_READ 0x977904c 1 0>,
<DCC_READ 0x9779054 1 0>,
<DCC_READ 0x977905c 1 0>,
<DCC_READ 0x977910c 2 0>,
<DCC_READ 0x9779204 1 0>,
<DCC_READ 0x977920c 1 0>,
<DCC_READ 0x9779238 1 0>,
<DCC_READ 0x9779240 1 0>,
<DCC_READ 0x977926c 1 0>,
<DCC_READ 0x9779394 1 0>,
<DCC_READ 0x977939c 1 0>,
<DCC_READ 0x9779704 1 0>,
<DCC_READ 0x977970c 1 0>,
<DCC_READ 0x910d100 3 0>,
<DCC_READ 0x914d100 3 0>,
<DCC_READ 0x918d100 4 0>,
<DCC_READ 0x91a5100 1 0>,
<DCC_READ 0x91ad100 1 0>,
<DCC_READ 0x610110 5 0>,
<DCC_WRITE 0x06e0a00c 0x00600007 1>,
<DCC_WRITE 0x06e0a01c 0x00136800 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136810 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136820 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136830 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136840 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136850 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136860 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136870 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003e9a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c0a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d1a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003e8a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003eea0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b1a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a014 0x0002000c 1>,
<DCC_WRITE 0x06e0a01c 0x000368b0 1>,
<DCC_WRITE 0x06e0a01c 0x00000ba8 1>,
<DCC_WRITE 0x06e0a01c 0x0013b6a0 1>,
<DCC_WRITE 0x06e0a01c 0x00f1e000 1>,
<DCC_WRITE 0x06e0a008 0x00000007 1>,
<DCC_READ 0x09067e00 124 0>;
};
link_list2 {
qcom,curr-link-list = <4>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0x9050078 1 0>,
<DCC_READ 0x9050110 8 0>,
<DCC_READ 0x9080058 2 0>,
<DCC_READ 0x90800c8 1 0>,
<DCC_READ 0x90800d4 1 0>,
<DCC_READ 0x90800e0 1 0>,
<DCC_READ 0x90800ec 1 0>,
<DCC_READ 0x90800f8 1 0>,
<DCC_READ 0x9084030 1 0>,
<DCC_READ 0x9084038 2 0>,
<DCC_READ 0x90840e4 1 0>,
<DCC_READ 0x90840f4 1 0>,
<DCC_READ 0x9084104 2 0>,
<DCC_READ 0x9084194 1 0>,
<DCC_READ 0x9084804 1 0>,
<DCC_READ 0x908480c 1 0>,
<DCC_READ 0x9084844 1 0>,
<DCC_READ 0x9084850 2 0>,
<DCC_READ 0x9084860 3 0>,
<DCC_READ 0x9084888 1 0>,
<DCC_READ 0x908488c 1 0>,
<DCC_READ 0x9084900 1 0>,
<DCC_READ 0x908409c 1 0>,
<DCC_READ 0x90840a0 1 0>,
<DCC_READ 0x908426c 1 0>,
<DCC_READ 0x908439c 1 0>,
<DCC_READ 0x9085124 1 0>,
<DCC_READ 0x90ba280 1 0>,
<DCC_READ 0x90ba288 7 0>,
<DCC_READ 0x9258610 4 0>,
<DCC_READ 0x92d8610 4 0>,
<DCC_READ 0x9358610 4 0>,
<DCC_READ 0x93d8610 4 0>,
<DCC_READ 0x9220344 8 0>,
<DCC_READ 0x9220370 6 0>,
<DCC_READ 0x9220480 1 0>,
<DCC_READ 0x9222400 1 0>,
<DCC_READ 0x922240c 1 0>,
<DCC_READ 0x9223214 2 0>,
<DCC_READ 0x9223220 3 0>,
<DCC_READ 0x9223308 1 0>,
<DCC_READ 0x9223318 1 0>,
<DCC_READ 0x9232100 1 0>,
<DCC_READ 0x9236040 6 0>,
<DCC_READ 0x92360b0 1 0>,
<DCC_READ 0x923a004 4 0>,
<DCC_READ 0x923e030 2 0>,
<DCC_READ 0x9241000 1 0>,
<DCC_READ 0x9242028 1 0>,
<DCC_READ 0x9242044 3 0>,
<DCC_READ 0x9242070 1 0>,
<DCC_READ 0x9248030 1 0>,
<DCC_READ 0x9248048 8 0>,
<DCC_READ 0x92a0344 8 0>,
<DCC_READ 0x92a0370 6 0>,
<DCC_READ 0x92a0480 1 0>,
<DCC_READ 0x92a2400 1 0>,
<DCC_READ 0x92a240c 1 0>,
<DCC_READ 0x92a3214 2 0>,
<DCC_READ 0x92a3220 3 0>,
<DCC_READ 0x92a3308 1 0>,
<DCC_READ 0x92a3318 1 0>,
<DCC_READ 0x92b2100 1 0>,
<DCC_READ 0x92b6040 6 0>,
<DCC_READ 0x92b60b0 1 0>,
<DCC_READ 0x92ba004 4 0>,
<DCC_READ 0x92be030 2 0>,
<DCC_READ 0x92c1000 1 0>,
<DCC_READ 0x92c2028 1 0>,
<DCC_READ 0x92c2044 3 0>,
<DCC_READ 0x92c2070 1 0>,
<DCC_READ 0x92c8030 1 0>,
<DCC_READ 0x92c8048 8 0>,
<DCC_READ 0x9320344 8 0>,
<DCC_READ 0x9320370 6 0>,
<DCC_READ 0x9320480 1 0>,
<DCC_READ 0x9322400 1 0>,
<DCC_READ 0x932240c 1 0>,
<DCC_READ 0x9323214 2 0>,
<DCC_READ 0x9323220 3 0>,
<DCC_READ 0x9323308 1 0>,
<DCC_READ 0x9323318 1 0>,
<DCC_READ 0x9332100 1 0>,
<DCC_READ 0x9336040 6 0>,
<DCC_READ 0x93360b0 1 0>,
<DCC_READ 0x933a004 4 0>,
<DCC_READ 0x933e030 2 0>,
<DCC_READ 0x9341000 1 0>,
<DCC_READ 0x9342028 1 0>,
<DCC_READ 0x9342044 3 0>,
<DCC_READ 0x9342070 1 0>,
<DCC_READ 0x9348030 1 0>,
<DCC_READ 0x9348048 8 0>,
<DCC_READ 0x93a0344 8 0>,
<DCC_READ 0x93a0370 6 0>,
<DCC_READ 0x93a0480 1 0>,
<DCC_READ 0x93a2400 1 0>,
<DCC_READ 0x93a240c 1 0>,
<DCC_READ 0x93a3214 2 0>,
<DCC_READ 0x93a3220 3 0>,
<DCC_READ 0x93a3308 1 0>,
<DCC_READ 0x93a3318 1 0>,
<DCC_READ 0x93b2100 1 0>,
<DCC_READ 0x93b6040 6 0>,
<DCC_READ 0x93b60b0 1 0>,
<DCC_READ 0x93ba004 4 0>,
<DCC_READ 0x93be030 2 0>,
<DCC_READ 0x93c1000 1 0>,
<DCC_READ 0x93c2028 1 0>,
<DCC_READ 0x93c2044 3 0>,
<DCC_READ 0x93c2070 1 0>,
<DCC_READ 0x93c8030 1 0>,
<DCC_READ 0x93c8048 8 0>,
<DCC_READ 0x9270080 1 0>,
<DCC_READ 0x9270310 1 0>,
<DCC_READ 0x9270400 1 0>,
<DCC_READ 0x9270410 6 0>,
<DCC_READ 0x9270430 1 0>,
<DCC_READ 0x9270440 1 0>,
<DCC_READ 0x9270448 1 0>,
<DCC_READ 0x92704a0 1 0>,
<DCC_READ 0x92704b0 1 0>,
<DCC_READ 0x92704b8 2 0>,
<DCC_READ 0x92704d0 2 0>,
<DCC_READ 0x9271400 1 0>,
<DCC_READ 0x9271408 1 0>,
<DCC_READ 0x927341c 1 0>,
<DCC_READ 0x92753b0 1 0>,
<DCC_READ 0x9275804 1 0>,
<DCC_READ 0x9275c1c 1 0>,
<DCC_READ 0x9275c2c 1 0>,
<DCC_READ 0x9275c38 1 0>,
<DCC_READ 0x9276418 2 0>,
<DCC_READ 0x9279100 1 0>,
<DCC_READ 0x9279110 1 0>,
<DCC_READ 0x9279120 1 0>,
<DCC_READ 0x9279180 2 0>,
<DCC_READ 0x92f0080 1 0>,
<DCC_READ 0x92f0310 1 0>,
<DCC_READ 0x92f0400 1 0>,
<DCC_READ 0x92f0410 6 0>,
<DCC_READ 0x92f0430 1 0>,
<DCC_READ 0x92f0440 1 0>,
<DCC_READ 0x92f0448 1 0>,
<DCC_READ 0x92f04a0 1 0>,
<DCC_READ 0x92f04b0 1 0>,
<DCC_READ 0x92f04b8 2 0>,
<DCC_READ 0x92f04d0 2 0>,
<DCC_READ 0x92f1400 1 0>,
<DCC_READ 0x92f1408 1 0>,
<DCC_READ 0x92f341c 1 0>,
<DCC_READ 0x92f53b0 1 0>,
<DCC_READ 0x92f5804 1 0>,
<DCC_READ 0x92f5c1c 1 0>,
<DCC_READ 0x92f5c2c 1 0>,
<DCC_READ 0x92f5c38 1 0>,
<DCC_READ 0x92f6418 2 0>,
<DCC_READ 0x92f9100 1 0>,
<DCC_READ 0x92f9110 1 0>,
<DCC_READ 0x92f9120 1 0>,
<DCC_READ 0x92f9180 2 0>,
<DCC_READ 0x9370080 1 0>,
<DCC_READ 0x9370310 1 0>,
<DCC_READ 0x9370400 1 0>,
<DCC_READ 0x9370410 6 0>,
<DCC_READ 0x9370430 1 0>,
<DCC_READ 0x9370440 1 0>,
<DCC_READ 0x9370448 1 0>,
<DCC_READ 0x93704a0 1 0>,
<DCC_READ 0x93704b0 1 0>,
<DCC_READ 0x93704b8 2 0>,
<DCC_READ 0x93704d0 2 0>,
<DCC_READ 0x9371400 1 0>,
<DCC_READ 0x9371408 1 0>,
<DCC_READ 0x937341c 1 0>,
<DCC_READ 0x93753b0 1 0>,
<DCC_READ 0x9375804 1 0>,
<DCC_READ 0x9375c1c 1 0>,
<DCC_READ 0x9375c2c 1 0>,
<DCC_READ 0x9375c38 1 0>,
<DCC_READ 0x9376418 2 0>,
<DCC_READ 0x9379100 1 0>,
<DCC_READ 0x9379110 1 0>,
<DCC_READ 0x9379120 1 0>,
<DCC_READ 0x9379180 2 0>,
<DCC_READ 0x93f0080 1 0>,
<DCC_READ 0x93f0310 1 0>,
<DCC_READ 0x93f0400 1 0>,
<DCC_READ 0x93f0410 6 0>,
<DCC_READ 0x93f0430 1 0>,
<DCC_READ 0x93f0440 1 0>,
<DCC_READ 0x93f0448 1 0>,
<DCC_READ 0x93f04a0 1 0>,
<DCC_READ 0x93f04b0 1 0>,
<DCC_READ 0x93f04b8 2 0>,
<DCC_READ 0x93f04d0 2 0>,
<DCC_READ 0x93f1400 1 0>,
<DCC_READ 0x93f1408 1 0>,
<DCC_READ 0x93f341c 1 0>,
<DCC_READ 0x93f53b0 1 0>,
<DCC_READ 0x93f5804 1 0>,
<DCC_READ 0x93f5c1c 1 0>,
<DCC_READ 0x93f5c2c 1 0>,
<DCC_READ 0x93f5c38 1 0>,
<DCC_READ 0x93f6418 2 0>,
<DCC_READ 0x93f9100 1 0>,
<DCC_READ 0x93f9110 1 0>,
<DCC_READ 0x93f9120 1 0>,
<DCC_READ 0x93f9180 2 0>,
<DCC_READ 0x9260080 1 0>,
<DCC_READ 0x9260400 1 0>,
<DCC_READ 0x9260410 3 0>,
<DCC_READ 0x9260420 2 0>,
<DCC_READ 0x9260430 1 0>,
<DCC_READ 0x9260440 1 0>,
<DCC_READ 0x9260448 1 0>,
<DCC_READ 0x92604a0 1 0>,
<DCC_READ 0x92604b0 1 0>,
<DCC_READ 0x92604b8 2 0>,
<DCC_READ 0x92604d0 2 0>,
<DCC_READ 0x9261400 1 0>,
<DCC_READ 0x9263410 1 0>,
<DCC_READ 0x92653b0 1 0>,
<DCC_READ 0x9265804 1 0>,
<DCC_READ 0x9265b1c 1 0>,
<DCC_READ 0x9265b2c 1 0>,
<DCC_READ 0x9265b38 1 0>,
<DCC_READ 0x9269100 1 0>,
<DCC_READ 0x9269108 1 0>,
<DCC_READ 0x9269110 1 0>,
<DCC_READ 0x9269118 1 0>,
<DCC_READ 0x9269120 1 0>,
<DCC_READ 0x9269180 2 0>,
<DCC_READ 0x92e0080 1 0>,
<DCC_READ 0x92e0400 1 0>,
<DCC_READ 0x92e0410 3 0>,
<DCC_READ 0x92e0420 2 0>,
<DCC_READ 0x92e0430 1 0>,
<DCC_READ 0x92e0440 1 0>,
<DCC_READ 0x92e0448 1 0>,
<DCC_READ 0x92e04a0 1 0>,
<DCC_READ 0x92e04b0 1 0>,
<DCC_READ 0x92e04b8 2 0>,
<DCC_READ 0x92e04d0 2 0>,
<DCC_READ 0x92e1400 1 0>,
<DCC_READ 0x92e3410 1 0>,
<DCC_READ 0x92e53b0 1 0>,
<DCC_READ 0x92e5804 1 0>,
<DCC_READ 0x92e5b1c 1 0>,
<DCC_READ 0x92e5b2c 1 0>,
<DCC_READ 0x92e5b38 1 0>,
<DCC_READ 0x92e9100 1 0>,
<DCC_READ 0x92e9108 1 0>,
<DCC_READ 0x92e9110 1 0>,
<DCC_READ 0x92e9118 1 0>,
<DCC_READ 0x92e9120 1 0>,
<DCC_READ 0x92e9180 2 0>,
<DCC_READ 0x9360080 1 0>,
<DCC_READ 0x9360400 1 0>,
<DCC_READ 0x9360410 3 0>,
<DCC_READ 0x9360420 2 0>,
<DCC_READ 0x9360430 1 0>,
<DCC_READ 0x9360440 1 0>,
<DCC_READ 0x9360448 1 0>,
<DCC_READ 0x93604a0 1 0>,
<DCC_READ 0x93604b0 1 0>,
<DCC_READ 0x93604b8 2 0>,
<DCC_READ 0x93604d0 2 0>,
<DCC_READ 0x9361400 1 0>,
<DCC_READ 0x9363410 1 0>,
<DCC_READ 0x93653b0 1 0>,
<DCC_READ 0x9365804 1 0>,
<DCC_READ 0x9365b1c 1 0>,
<DCC_READ 0x9365b2c 1 0>,
<DCC_READ 0x9365b38 1 0>,
<DCC_READ 0x9369100 1 0>,
<DCC_READ 0x9369108 1 0>,
<DCC_READ 0x9369110 1 0>,
<DCC_READ 0x9369118 1 0>,
<DCC_READ 0x9369120 1 0>,
<DCC_READ 0x9369180 2 0>,
<DCC_READ 0x93e0080 1 0>,
<DCC_READ 0x93e0400 1 0>,
<DCC_READ 0x93e0410 3 0>,
<DCC_READ 0x93e0420 2 0>,
<DCC_READ 0x93e0430 1 0>,
<DCC_READ 0x93e0440 1 0>,
<DCC_READ 0x93e0448 1 0>,
<DCC_READ 0x93e04a0 1 0>,
<DCC_READ 0x93e04b0 1 0>,
<DCC_READ 0x93e04b8 2 0>,
<DCC_READ 0x93e04d0 2 0>,
<DCC_READ 0x93e1400 1 0>,
<DCC_READ 0x93e3410 1 0>,
<DCC_READ 0x93e53b0 1 0>,
<DCC_READ 0x93e5804 1 0>,
<DCC_READ 0x93e5b1c 1 0>,
<DCC_READ 0x93e5b2c 1 0>,
<DCC_READ 0x93e5b38 1 0>,
<DCC_READ 0x93e9100 1 0>,
<DCC_READ 0x93e9108 1 0>,
<DCC_READ 0x93e9110 1 0>,
<DCC_READ 0x93e9118 1 0>,
<DCC_READ 0x93e9120 1 0>,
<DCC_READ 0x93e9180 2 0>,
<DCC_READ 0x96b0868 1 0>,
<DCC_READ 0x96b0870 1 0>,
<DCC_READ 0x96b1004 1 0>,
<DCC_READ 0x96b100c 1 0>,
<DCC_READ 0x96b1014 1 0>,
<DCC_READ 0x96b1204 1 0>,
<DCC_READ 0x96b120c 1 0>,
<DCC_READ 0x96b1214 1 0>,
<DCC_READ 0x96b1504 1 0>,
<DCC_READ 0x96b150c 1 0>,
<DCC_READ 0x96b1514 1 0>,
<DCC_READ 0x96b1604 1 0>,
<DCC_READ 0x96b8100 1 0>,
<DCC_READ 0x96b813c 1 0>,
<DCC_READ 0x96b8500 1 0>,
<DCC_READ 0x96b853c 1 0>,
<DCC_READ 0x96b8a04 1 0>,
<DCC_READ 0x96b8a18 1 0>,
<DCC_READ 0x96b8ea8 1 0>,
<DCC_READ 0x96b9044 1 0>,
<DCC_READ 0x96b904c 1 0>,
<DCC_READ 0x96b9054 1 0>,
<DCC_READ 0x96b905c 1 0>,
<DCC_READ 0x96b910c 2 0>,
<DCC_READ 0x96b9204 1 0>,
<DCC_READ 0x96b920c 1 0>,
<DCC_READ 0x96b9238 1 0>,
<DCC_READ 0x96b9240 1 0>,
<DCC_READ 0x96b926c 1 0>,
<DCC_READ 0x96b9394 1 0>,
<DCC_READ 0x96b939c 1 0>,
<DCC_READ 0x96b9704 1 0>,
<DCC_READ 0x96b970c 1 0>,
<DCC_READ 0x96f0868 1 0>,
<DCC_READ 0x96f0870 1 0>,
<DCC_READ 0x96f1004 1 0>,
<DCC_READ 0x96f100c 1 0>,
<DCC_READ 0x96f1014 1 0>,
<DCC_READ 0x96f1204 1 0>,
<DCC_READ 0x96f120c 1 0>,
<DCC_READ 0x96f1214 1 0>,
<DCC_READ 0x96f1504 1 0>,
<DCC_READ 0x96f150c 1 0>,
<DCC_READ 0x96f1514 1 0>,
<DCC_READ 0x96f1604 1 0>,
<DCC_READ 0x96f8100 1 0>,
<DCC_READ 0x96f813c 1 0>,
<DCC_READ 0x96f8500 1 0>,
<DCC_READ 0x96f853c 1 0>,
<DCC_READ 0x96f8a04 1 0>,
<DCC_READ 0x96f8a18 1 0>,
<DCC_READ 0x96f8ea8 1 0>,
<DCC_READ 0x96f9044 1 0>,
<DCC_READ 0x96f904c 1 0>,
<DCC_READ 0x96f9054 1 0>,
<DCC_READ 0x96f905c 1 0>,
<DCC_READ 0x96f910c 2 0>,
<DCC_READ 0x96f9204 1 0>,
<DCC_READ 0x96f920c 1 0>,
<DCC_READ 0x96f9238 1 0>,
<DCC_READ 0x96f9240 1 0>,
<DCC_READ 0x96f926c 1 0>,
<DCC_READ 0x96f9394 1 0>,
<DCC_READ 0x96f939c 1 0>,
<DCC_READ 0x96f9704 1 0>,
<DCC_READ 0x96f970c 1 0>,
<DCC_READ 0x9730868 1 0>,
<DCC_READ 0x9730870 1 0>,
<DCC_READ 0x9731004 1 0>,
<DCC_READ 0x973100c 1 0>,
<DCC_READ 0x9731014 1 0>,
<DCC_READ 0x9731204 1 0>,
<DCC_READ 0x973120c 1 0>,
<DCC_READ 0x9731214 1 0>,
<DCC_READ 0x9731504 1 0>,
<DCC_READ 0x973150c 1 0>,
<DCC_READ 0x9731514 1 0>,
<DCC_READ 0x9731604 1 0>,
<DCC_READ 0x9738100 1 0>,
<DCC_READ 0x973813c 1 0>,
<DCC_READ 0x9738500 1 0>,
<DCC_READ 0x973853c 1 0>,
<DCC_READ 0x9738a04 1 0>,
<DCC_READ 0x9738a18 1 0>,
<DCC_READ 0x9738ea8 1 0>,
<DCC_READ 0x9739044 1 0>,
<DCC_READ 0x973904c 1 0>,
<DCC_READ 0x9739054 1 0>,
<DCC_READ 0x973905c 1 0>,
<DCC_READ 0x973910c 2 0>,
<DCC_READ 0x9739204 1 0>,
<DCC_READ 0x973920c 1 0>,
<DCC_READ 0x9739238 1 0>,
<DCC_READ 0x9739240 1 0>,
<DCC_READ 0x973926c 1 0>,
<DCC_READ 0x9739394 1 0>,
<DCC_READ 0x973939c 1 0>,
<DCC_READ 0x9739704 1 0>,
<DCC_READ 0x973970c 1 0>,
<DCC_READ 0x9770868 1 0>,
<DCC_READ 0x9770870 1 0>,
<DCC_READ 0x9771004 1 0>,
<DCC_READ 0x977100c 1 0>,
<DCC_READ 0x9771014 1 0>,
<DCC_READ 0x9771204 1 0>,
<DCC_READ 0x977120c 1 0>,
<DCC_READ 0x9771214 1 0>,
<DCC_READ 0x9771504 1 0>,
<DCC_READ 0x977150c 1 0>,
<DCC_READ 0x9771514 1 0>,
<DCC_READ 0x9771604 1 0>,
<DCC_READ 0x9778100 1 0>,
<DCC_READ 0x977813c 1 0>,
<DCC_READ 0x9778500 1 0>,
<DCC_READ 0x977853c 1 0>,
<DCC_READ 0x9778a04 1 0>,
<DCC_READ 0x9778a18 1 0>,
<DCC_READ 0x9778ea8 1 0>,
<DCC_READ 0x9779044 1 0>,
<DCC_READ 0x977904c 1 0>,
<DCC_READ 0x9779054 1 0>,
<DCC_READ 0x977905c 1 0>,
<DCC_READ 0x977910c 2 0>,
<DCC_READ 0x9779204 1 0>,
<DCC_READ 0x977920c 1 0>,
<DCC_READ 0x9779238 1 0>,
<DCC_READ 0x9779240 1 0>,
<DCC_READ 0x977926c 1 0>,
<DCC_READ 0x9779394 1 0>,
<DCC_READ 0x977939c 1 0>,
<DCC_READ 0x9779704 1 0>,
<DCC_READ 0x977970c 1 0>,
<DCC_READ 0x910d100 3 0>,
<DCC_READ 0x914d100 3 0>,
<DCC_READ 0x918d100 4 0>,
<DCC_READ 0x91a5100 1 0>,
<DCC_READ 0x91ad100 1 0>,
<DCC_READ 0x610110 5 0>,
<DCC_WRITE 0x06e0a00c 0x00600007 1>,
<DCC_WRITE 0x06e0a01c 0x00136800 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136810 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136820 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136830 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136840 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136850 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136860 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136870 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003e9a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c0a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d1a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003e8a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003eea0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b1a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a014 0x0002000c 1>,
<DCC_WRITE 0x06e0a01c 0x000368b0 1>,
<DCC_WRITE 0x06e0a01c 0x00000ba8 1>,
<DCC_WRITE 0x06e0a01c 0x0013b6a0 1>,
<DCC_WRITE 0x06e0a01c 0x00f1e000 1>,
<DCC_WRITE 0x06e0a008 0x00000007 1>,
<DCC_READ 0x09067e00 124 0>;
};
link_list3 {
qcom,curr-link-list = <3>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0x18200400 1 0>,
<DCC_READ 0x18200404 1 0>,
<DCC_READ 0x18200408 1 0>,
<DCC_READ 0x18200038 1 0>,
<DCC_READ 0x18200040 1 0>,
<DCC_READ 0x18200048 1 0>,
<DCC_READ 0x18220038 1 0>,
<DCC_READ 0x18220040 1 0>,
<DCC_READ 0x182200d0 1 0>,
<DCC_READ 0x18200030 1 0>,
<DCC_READ 0x18200010 1 0>,
<DCC_READ 0x1822000c 1 0>,
<DCC_READ 0x18220d14 1 0>,
<DCC_READ 0x18220fb4 1 0>,
<DCC_READ 0x18221254 1 0>,
<DCC_READ 0x182214f4 1 0>,
<DCC_READ 0x18221794 1 0>,
<DCC_READ 0x18221a34 1 0>,
<DCC_READ 0x18221cd4 1 0>,
<DCC_READ 0x18221f74 1 0>,
<DCC_READ 0x18220d18 1 0>,
<DCC_READ 0x18220fb8 1 0>,
<DCC_READ 0x18221258 1 0>,
<DCC_READ 0x182214f8 1 0>,
<DCC_READ 0x18221798 1 0>,
<DCC_READ 0x18221a38 1 0>,
<DCC_READ 0x18221cd8 1 0>,
<DCC_READ 0x18221f78 1 0>,
<DCC_READ 0x18220d00 1 0>,
<DCC_READ 0x18220d04 1 0>,
<DCC_READ 0x18220d1c 1 0>,
<DCC_READ 0x18220fbc 1 0>,
<DCC_READ 0x1822125c 1 0>,
<DCC_READ 0x182214fc 1 0>,
<DCC_READ 0x1822179c 1 0>,
<DCC_READ 0x18221a3c 1 0>,
<DCC_READ 0x18221cdc 1 0>,
<DCC_READ 0x18221f7c 1 0>,
<DCC_READ 0x18221274 1 0>,
<DCC_READ 0x18221288 1 0>,
<DCC_READ 0x1822129c 1 0>,
<DCC_READ 0x182212b0 1 0>,
<DCC_READ 0x182212c4 1 0>,
<DCC_READ 0x182212d8 1 0>,
<DCC_READ 0x182212ec 1 0>,
<DCC_READ 0x18221300 1 0>,
<DCC_READ 0x18221314 1 0>,
<DCC_READ 0x18221328 1 0>,
<DCC_READ 0x1822133c 1 0>,
<DCC_READ 0x18221350 1 0>,
<DCC_READ 0x18221364 1 0>,
<DCC_READ 0x18221378 1 0>,
<DCC_READ 0x1822138c 1 0>,
<DCC_READ 0x182213a0 1 0>,
<DCC_READ 0x18221514 1 0>,
<DCC_READ 0x18221528 1 0>,
<DCC_READ 0x1822153c 1 0>,
<DCC_READ 0x18221550 1 0>,
<DCC_READ 0x18221564 1 0>,
<DCC_READ 0x18221578 1 0>,
<DCC_READ 0x1822158c 1 0>,
<DCC_READ 0x182215a0 1 0>,
<DCC_READ 0x182215b4 1 0>,
<DCC_READ 0x182215c8 1 0>,
<DCC_READ 0x182215dc 1 0>,
<DCC_READ 0x182215f0 1 0>,
<DCC_READ 0x18221604 1 0>,
<DCC_READ 0x18221618 1 0>,
<DCC_READ 0x1822162c 1 0>,
<DCC_READ 0x18221640 1 0>,
<DCC_READ 0x182217b4 1 0>,
<DCC_READ 0x182217c8 1 0>,
<DCC_READ 0x182217dc 1 0>,
<DCC_READ 0x182217f0 1 0>,
<DCC_READ 0x18221804 1 0>,
<DCC_READ 0x18221818 1 0>,
<DCC_READ 0x1822182c 1 0>,
<DCC_READ 0x18221840 1 0>,
<DCC_READ 0x18221854 1 0>,
<DCC_READ 0x18221868 1 0>,
<DCC_READ 0x1822187c 1 0>,
<DCC_READ 0x18221890 1 0>,
<DCC_READ 0x182218a4 1 0>,
<DCC_READ 0x182218b8 1 0>,
<DCC_READ 0x182218cc 1 0>,
<DCC_READ 0x182218e0 1 0>,
<DCC_READ 0x18221a54 1 0>,
<DCC_READ 0x18221a68 1 0>,
<DCC_READ 0x18221a7c 1 0>,
<DCC_READ 0x18221a90 1 0>,
<DCC_READ 0x18221aa4 1 0>,
<DCC_READ 0x18221ab8 1 0>,
<DCC_READ 0x18221acc 1 0>,
<DCC_READ 0x18221ae0 1 0>,
<DCC_READ 0x18221af4 1 0>,
<DCC_READ 0x18221b08 1 0>,
<DCC_READ 0x18221b1c 1 0>,
<DCC_READ 0x18221b30 1 0>,
<DCC_READ 0x18221b44 1 0>,
<DCC_READ 0x18221b58 1 0>,
<DCC_READ 0x18221b6c 1 0>,
<DCC_READ 0x18221b80 1 0>,
<DCC_READ 0x18221cf4 1 0>,
<DCC_READ 0x18221d08 1 0>,
<DCC_READ 0x18221d1c 1 0>,
<DCC_READ 0x18221d30 1 0>,
<DCC_READ 0x18221d44 1 0>,
<DCC_READ 0x18221d58 1 0>,
<DCC_READ 0x18221d6c 1 0>,
<DCC_READ 0x18221d80 1 0>,
<DCC_READ 0x18221d94 1 0>,
<DCC_READ 0x18221da8 1 0>,
<DCC_READ 0x18221dbc 1 0>,
<DCC_READ 0x18221dd0 1 0>,
<DCC_READ 0x18221de4 1 0>,
<DCC_READ 0x18221df8 1 0>,
<DCC_READ 0x18221e0c 1 0>,
<DCC_READ 0x18221e20 1 0>,
<DCC_READ 0x18221f94 1 0>,
<DCC_READ 0x18221fa8 1 0>,
<DCC_READ 0x18221fbc 1 0>,
<DCC_READ 0x18221fd0 1 0>,
<DCC_READ 0x18221fe4 1 0>,
<DCC_READ 0x18221ff8 1 0>,
<DCC_READ 0x1822200c 1 0>,
<DCC_READ 0x18222020 1 0>,
<DCC_READ 0x18222034 1 0>,
<DCC_READ 0x18222048 1 0>,
<DCC_READ 0x1822205c 1 0>,
<DCC_READ 0x18222070 1 0>,
<DCC_READ 0x18222084 1 0>,
<DCC_READ 0x18222098 1 0>,
<DCC_READ 0x182220ac 1 0>,
<DCC_READ 0x182220c0 1 0>,
<DCC_READ 0x18221278 1 0>,
<DCC_READ 0x1822128c 1 0>,
<DCC_READ 0x182212a0 1 0>,
<DCC_READ 0x182212b4 1 0>,
<DCC_READ 0x182212c8 1 0>,
<DCC_READ 0x182212dc 1 0>,
<DCC_READ 0x182212f0 1 0>,
<DCC_READ 0x18221304 1 0>,
<DCC_READ 0x18221318 1 0>,
<DCC_READ 0x1822132c 1 0>,
<DCC_READ 0x18221340 1 0>,
<DCC_READ 0x18221354 1 0>,
<DCC_READ 0x18221368 1 0>,
<DCC_READ 0x1822137c 1 0>,
<DCC_READ 0x18221390 1 0>,
<DCC_READ 0x182213a4 1 0>,
<DCC_READ 0x18221518 1 0>,
<DCC_READ 0x1822152c 1 0>,
<DCC_READ 0x18221540 1 0>,
<DCC_READ 0x18221554 1 0>,
<DCC_READ 0x18221568 1 0>,
<DCC_READ 0x1822157c 1 0>,
<DCC_READ 0x18221590 1 0>,
<DCC_READ 0x182215a4 1 0>,
<DCC_READ 0x182215b8 1 0>,
<DCC_READ 0x182215cc 1 0>,
<DCC_READ 0x182215e0 1 0>,
<DCC_READ 0x182215f4 1 0>,
<DCC_READ 0x18221608 1 0>,
<DCC_READ 0x1822161c 1 0>,
<DCC_READ 0x18221630 1 0>,
<DCC_READ 0x18221644 1 0>,
<DCC_READ 0x182217b8 1 0>,
<DCC_READ 0x182217cc 1 0>,
<DCC_READ 0x182217e0 1 0>,
<DCC_READ 0x182217f4 1 0>,
<DCC_READ 0x18221808 1 0>,
<DCC_READ 0x1822181c 1 0>,
<DCC_READ 0x18221830 1 0>,
<DCC_READ 0x18221844 1 0>,
<DCC_READ 0x18221858 1 0>,
<DCC_READ 0x1822186c 1 0>,
<DCC_READ 0x18221880 1 0>,
<DCC_READ 0x18221894 1 0>,
<DCC_READ 0x182218a8 1 0>,
<DCC_READ 0x182218bc 1 0>,
<DCC_READ 0x182218d0 1 0>,
<DCC_READ 0x182218e4 1 0>,
<DCC_READ 0x18221a58 1 0>,
<DCC_READ 0x18221a6c 1 0>,
<DCC_READ 0x18221a80 1 0>,
<DCC_READ 0x18221a94 1 0>,
<DCC_READ 0x18221aa8 1 0>,
<DCC_READ 0x18221abc 1 0>,
<DCC_READ 0x18221ad0 1 0>,
<DCC_READ 0x18221ae4 1 0>,
<DCC_READ 0x18221af8 1 0>,
<DCC_READ 0x18221b0c 1 0>,
<DCC_READ 0x18221b20 1 0>,
<DCC_READ 0x18221b34 1 0>,
<DCC_READ 0x18221b48 1 0>,
<DCC_READ 0x18221b5c 1 0>,
<DCC_READ 0x18221b70 1 0>,
<DCC_READ 0x18221b84 1 0>,
<DCC_READ 0x18221cf8 1 0>,
<DCC_READ 0x18221d0c 1 0>,
<DCC_READ 0x18221d20 1 0>,
<DCC_READ 0x18221d34 1 0>,
<DCC_READ 0x18221d48 1 0>,
<DCC_READ 0x18221d5c 1 0>,
<DCC_READ 0x18221d70 1 0>,
<DCC_READ 0x18221d84 1 0>,
<DCC_READ 0x18221d98 1 0>,
<DCC_READ 0x18221dac 1 0>,
<DCC_READ 0x18221dc0 1 0>,
<DCC_READ 0x18221dd4 1 0>,
<DCC_READ 0x18221de8 1 0>,
<DCC_READ 0x18221dfc 1 0>,
<DCC_READ 0x18221e10 1 0>,
<DCC_READ 0x18221e24 1 0>,
<DCC_READ 0x18221f98 1 0>,
<DCC_READ 0x18221fac 1 0>,
<DCC_READ 0x18221fc0 1 0>,
<DCC_READ 0x18221fd4 1 0>,
<DCC_READ 0x18221fe8 1 0>,
<DCC_READ 0x18221ffc 1 0>,
<DCC_READ 0x18222010 1 0>,
<DCC_READ 0x18222024 1 0>,
<DCC_READ 0x18222038 1 0>,
<DCC_READ 0x1822204c 1 0>,
<DCC_READ 0x18222060 1 0>,
<DCC_READ 0x18222074 1 0>,
<DCC_READ 0x18222088 1 0>,
<DCC_READ 0x1822209c 1 0>,
<DCC_READ 0x182220b0 1 0>,
<DCC_READ 0x182220c4 1 0>;
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;
ranges = <0x0 0x146bf000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
dload_mode {
compatible = "qcom,dload-mode";
};
tlmm: pinctrl@f000000 {
compatible = "qcom,lahaina-pinctrl";
reg = <0x0F000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
};
ipcc_mproc: qcom,ipcc@408000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
qcom,svm_neuron_block {
compatible = "qcom,neuron-service";
#address-cells = <1>;
#size-cells = <0>;
protocol {
compatible = "qcom,neuron-protocol-block";
processes = "server";
};
application {
compatible = "qcom,neuron-block-server";
};
channel@0 {
compatible = "qcom,neuron-channel-haven-shmem";
reg = <0>;
class = "message-queue";
direction = "receive";
max-size = <0 65536>;
shared-buffer = <&chan0_shbuf>;
qcom,primary;
haven-label = <1>;
peer-name = <2>;
};
channel@1 {
compatible = "qcom,neuron-channel-haven-shmem";
reg = <1>;
class = "message-queue";
direction = "send";
max-size = <0 65536>;
shared-buffer = <&chan1_shbuf>;
qcom,primary;
haven-label = <2>;
peer-name = <2>;
};
};
qcom,qsee_ipc_irq_bridge {
compatible = "qcom,qsee-ipc-irq-bridge";
qcom,qsee-ipc-irq-spss {
qcom,dev-name = "qsee_ipc_irq_spss";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_TZ
IRQ_TYPE_EDGE_RISING>;
label = "spss";
};
};
qrtr-haven {
compatible = "qcom,qrtr-haven";
qcom,master;
haven-label = <3>;
peer-name = <2>;
shared-buffer = <&qrtr_shbuf>;
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
qcom,client_2 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <2>;
label = "modem";
};
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
memory-region = <&memshare_mem>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
};
};
clock_aop: qcom,aopclk {
compatible = "qcom,aop-qmp-clk";
#clock-cells = <1>;
mboxes = <&qmp_aop 0>;
mbox-names = "qdss_clk";
};
clock_gcc: qcom,gcc@100000 {
compatible = "qcom,lahaina-gcc", "syscon";
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_videocc: qcom,videocc@abf0000 {
compatible = "qcom,lahaina-videocc", "syscon";
reg = <0xabf0000 0x10000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_camcc: qcom,camcc@ad00000 {
compatible = "qcom,lahaina-camcc", "syscon";
reg = <0xad00000 0x10000>;
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_dispcc: qcom,dispcc@af00000 {
compatible = "qcom,lahaina-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_gpucc: qcom,gpucc@3d90000 {
compatible = "qcom,lahaina-gpucc", "syscon";
reg = <0x3d90000 0x9000>;
reg-names = "cc_base";
vdd_mx-supply = <&VDD_MXA_LEVEL>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
clock_mccc: syscon@90ba000 {
compatible = "syscon";
reg = <0x90ba000 0x54>;
};
clock_debugcc: qcom,cc-debug {
compatible = "qcom,lahaina-debugcc";
qcom,gcc = <&clock_gcc>;
qcom,videocc = <&clock_videocc>;
qcom,dispcc = <&clock_dispcc>;
qcom,camcc = <&clock_camcc>;
qcom,gpucc = <&clock_gpucc>;
qcom,apsscc = <&clock_apsscc>;
qcom,mccc = <&clock_mccc>;
clock-names = "xo_clk_src";
clocks = <&clock_rpmh RPMH_CXO_CLK>;
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
<0x18593000 0x1000>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
#freq-domain-cells = <2>;
};
/* CAM_CC GDSCs */
cam_cc_bps_gdsc: qcom,gdsc@ad07004 {
compatible = "qcom,gdsc";
reg = <0xad07004 0x4>;
regulator-name = "cam_cc_bps_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,support-hw-trigger;
qcom,retain-regs;
};
cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 {
compatible = "qcom,gdsc";
reg = <0xad0a004 0x4>;
regulator-name = "cam_cc_ife_0_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 {
compatible = "qcom,gdsc";
reg = <0xad0b004 0x4>;
regulator-name = "cam_cc_ife_1_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 {
compatible = "qcom,gdsc";
reg = <0xad0b070 0x4>;
regulator-name = "cam_cc_ife_2_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 {
compatible = "qcom,gdsc";
reg = <0xad08004 0x4>;
regulator-name = "cam_cc_ipe_0_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,support-hw-trigger;
qcom,retain-regs;
};
cam_cc_sbi_gdsc: qcom,gdsc@ad09004 {
compatible = "qcom,gdsc";
reg = <0xad09004 0x4>;
regulator-name = "cam_cc_sbi_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 {
compatible = "qcom,gdsc";
reg = <0xad0c120 0x4>;
regulator-name = "cam_cc_titan_top_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
/* DISP_CC GDSCs */
disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
compatible = "qcom,gdsc";
reg = <0xaf03000 0x4>;
regulator-name = "disp_cc_mdss_core_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,support-hw-trigger;
qcom,retain-regs;
proxy-supply = <&disp_cc_mdss_core_gdsc>;
qcom,proxy-consumer-enable;
};
gcc_apcs_gdsc_vote_ctrl: syscon@152128 {
compatible = "syscon";
reg = <0x152128 0x4>;
};
/* GCC GDSCs */
gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
compatible = "qcom,gdsc";
reg = <0x16b004 0x4>;
regulator-name = "gcc_pcie_0_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
};
gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
compatible = "qcom,gdsc";
reg = <0x18d004 0x4>;
regulator-name = "gcc_pcie_1_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
};
gcc_ufs_card_gdsc: qcom,gdsc@175004 {
compatible = "qcom,gdsc";
reg = <0x175004 0x4>;
regulator-name = "gcc_ufs_card_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
compatible = "qcom,gdsc";
reg = <0x177004 0x4>;
regulator-name = "gcc_ufs_phy_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
gcc_usb30_prim_gdsc: qcom,gdsc@10f004 {
compatible = "qcom,gdsc";
reg = <0x10f004 0x4>;
regulator-name = "gcc_usb30_prim_gdsc";
qcom,gds-timeout = <500>;
qcom,retain-regs;
};
gcc_usb30_sec_gdsc: qcom,gdsc@110004 {
compatible = "qcom,gdsc";
reg = <0x110004 0x4>;
regulator-name = "gcc_usb30_sec_gdsc";
qcom,gds-timeout = <500>;
qcom,retain-regs;
};
gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
compatible = "qcom,gdsc";
reg = <0x17d050 0x4>;
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
qcom,no-status-check-on-disable;
qcom,gds-timeout = <500>;
};
gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
compatible = "qcom,gdsc";
reg = <0x17d058 0x4>;
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
qcom,no-status-check-on-disable;
qcom,gds-timeout = <500>;
};
gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
compatible = "qcom,gdsc";
reg = <0x17d054 0x4>;
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
qcom,no-status-check-on-disable;
qcom,gds-timeout = <500>;
};
gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
compatible = "qcom,gdsc";
reg = <0x17d06c 0x4>;
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
qcom,no-status-check-on-disable;
qcom,gds-timeout = <500>;
};
/* GPU_CC GDSCs */
gpu_cc_cx_hw_ctrl: syscon@3d91540 {
compatible = "syscon";
reg = <0x3d91540 0x4>;
};
gpu_cc_cx_gdsc: qcom,gdsc@3d9106c {
compatible = "qcom,gdsc";
reg = <0x3d9106c 0x4>;
regulator-name = "gpu_cc_cx_gdsc";
hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,no-status-check-on-disable;
qcom,clk-dis-wait-val = <8>;
qcom,gds-timeout = <500>;
qcom,retain-regs;
};
gpu_cc_gx_domain_addr: syscon@3d9158c {
compatible = "syscon";
reg = <0x3d9158c 0x4>;
};
gpu_cc_gx_sw_reset: syscon@3d91008 {
compatible = "syscon";
reg = <0x3d91008 0x4>;
};
gpu_cc_gx_gdsc: qcom,gdsc@3d9100c {
compatible = "qcom,gdsc";
reg = <0x3d9100c 0x4>;
regulator-name = "gpu_cc_gx_gdsc";
qcom,gds-timeout = <500>;
domain-addr = <&gpu_cc_gx_domain_addr>;
sw-reset = <&gpu_cc_gx_sw_reset>;
parent-supply = <&VDD_GFX_LEVEL>;
vdd_parent-supply = <&VDD_GFX_LEVEL>;
qcom,reset-aon-logic;
qcom,retain-regs;
};
/* VIDEO_CC GDSCs */
video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 {
compatible = "qcom,gdsc";
reg = <0xabf0d18 0x4>;
regulator-name = "video_cc_mvs0_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,support-hw-trigger;
qcom,retain-regs;
};
video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 {
compatible = "qcom,gdsc";
reg = <0xabf0bf8 0x4>;
regulator-name = "video_cc_mvs0c_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 {
compatible = "qcom,gdsc";
reg = <0xabf0d98 0x4>;
regulator-name = "video_cc_mvs1_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,support-hw-trigger;
qcom,retain-regs;
};
video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 {
compatible = "qcom,gdsc";
reg = <0xabf0c98 0x4>;
regulator-name = "video_cc_mvs1c_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
vdd_parent-supply = <&VDD_MM_LEVEL>;
qcom,retain-regs;
};
thermal_zones: thermal-zones {
};
qmi_tmd: qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
};
cache-controller@9200000 {
compatible = "qcom,lahaina-llcc", "qcom,llcc-v2";
reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&clock_aop QDSS_CLK>;
clock-names = "qdss_clk";
};
qcom_scm {
compatible = "qcom,secure-chan-manager";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom-mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
};
qcom,chd {
compatible = "qcom,core-hang-detect";
label = "core";
qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058
0x18040058 0x18050058 0x18060058 0x18070058>;
qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060
0x18040060 0x18050060 0x18060060 0x18070060>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,lahaina-aggre1_noc";
reg = <0x016E0000 0x1f180>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
reg = <0x1700000 0x3d180>;
compatible = "qcom,lahaina-aggre2_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&clock_gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&clock_rpmh RPMH_IPA_CLK>;
};
clk_virt: interconnect {
compatible = "qcom,lahaina-clk_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect@1500000 {
reg = <0x1500000 0x28000>;
compatible = "qcom,lahaina-config_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect@90e0000 {
reg = <0x90e0000 0x5080>;
compatible = "qcom,lahaina-dc_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
reg = <0x9100000 0xb4000>;
compatible = "qcom,lahaina-gem_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
lpass_ag_noc: interconnect@3c40000 {
reg = <0x03c40000 0xf080>;
compatible = "qcom,lahaina-lpass_ag_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1580000 {
reg = <0x1580000 0x4>;
compatible = "qcom,lahaina-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
reg = <0x1740000 0x1f080>;
compatible = "qcom,lahaina-mmss_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
nsp_noc: interconnect@a0c0000 {
reg = <0x0a0c0000 0x10000>;
compatible = "qcom,lahaina-nsp_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
reg = <0x1680000 0x1EE00>;
compatible = "qcom,lahaina-system_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
epss_l3_cpu: l3_cpu@18590000 {
reg = <0x18590000 0x4000>;
compatible = "qcom,lahaina-epss-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_GPLL0>;
};
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x280000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
};
qcom_hwkm: hwkm@10c0000 {
compatible = "qcom,hwkm";
reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>;
reg-names = "km_master", "ice_slave";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&clock_rpmh RPMH_HWKM_CLK>;
qcom,op-freq-hz = <75000000>;
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe10>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_aux_clk";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x8000>,
<0x1d90000 0x9000>;
reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<1492582 0>, <102400 0>, /* HS G3 RA */
<2915200 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<1492582 0>, <204800 0>, /* HS G3 RA L2 */
<2915200 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<1492582 0>, <102400 0>, /* HS G3 RB */
<2915200 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;
resets = <&clock_gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0xE0 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
status = "disabled";
qos0 {
mask = <0xf0>;
vote = <44>;
};
qos1 {
mask = <0x0f>;
vote = <44>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <4>;
qcom,large-address-bus;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No Vote */
<0 0>, <0 0>,
/* 400 KB/s*/
<1046 1600>, <1600 1600>,
/* 20 MB/s */
<52286 80000>, <80000 80000>,
/* 25 MB/s */
<65360 100000>, <100000 100000>,
/* 50 MB/s */
<130718 200000>, <133320 133320>,
/* 100 MB/s */
<261438 200000>, <150000 150000>,
/* 200 MB/s */
<261438 400000>, <300000 300000>,
/* Max. bandwidth */
<1338562 4096000>, <1338562 4096000>;
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100750000 200000000 4294967295>;
qcom,restore-after-cx-collapse;
qcom,clk-rates = <400000 20000000 25000000
50000000 100000000 201500000>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
"SDR104";
qcom,devfreq,freq-table = <50000000 201500000>;
clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
<&clock_gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
0x2C010800 0x80040868>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
iommus = <&apps_smmu 0x4a0 0x0>;
dma-coherent;
qcom,iommu-dma = "bypass";
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <44>;
};
qos1 {
mask = <0xf0>;
vote = <44>;
};
};
kryo_erp: erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
qcom,disable-panic-on-ce;
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "aop_qmp";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0xc300000 0x400>;
reg-names = "msgram";
label = "aop";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
aop-msg-client {
compatible = "qcom,debugfs-qmp-client";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
interrupt-parent = <&sleepstate_smp2p_in>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,lahaina-pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
<59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
<69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0x1c00>;
qcom,drv-id = <0>;
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
disp_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};
sde_rsc_rpmh {
compatible = "qcom,sde-rsc-rpmh";
cell-index = <0>;
};
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
spmi_debug_bus: qcom,spmi-debug@6b12000 {
compatible = "qcom,spmi-pmic-arb-debug";
reg = <0x6b12000 0x60>, <0x7820a8 0x4>;
reg-names = "core", "fuse";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,fuse-disable-bit = <24>;
#address-cells = <2>;
#size-cells = <0>;
status = "disabled";
qcom,pmk8350-debug@0 {
compatible = "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350-debug@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350c-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350b-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmr735a-debug@4 {
compatible = "qcom,spmi-pmic";
reg = <4 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmr735b-debug@5 {
compatible = "qcom,spmi-pmic";
reg = <5 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
qcom,msm-cdsp-loader {
compatible = "qcom,cdsp-loader";
qcom,proc-img-to-load = "cdsp";
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
restrict-access;
};
msm_fastrpc: qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,adsp-remoteheap-vmid = <22 37>;
qcom,fastrpc-adsp-audio-pdr;
qcom,fastrpc-adsp-sensors-pdr;
qcom,rpc-latency-us = <235>;
qcom,fastrpc-gids = <2908>;
qcom,qos-cores = <0 1 2 3>;
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2161 0x0400>,
<&apps_smmu 0x1181 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2162 0x0400>,
<&apps_smmu 0x1182 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2163 0x0400>,
<&apps_smmu 0x1183 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2164 0x0400>,
<&apps_smmu 0x1184 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2165 0x0400>,
<&apps_smmu 0x1185 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2166 0x0400>,
<&apps_smmu 0x1186 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2167 0x0400>,
<&apps_smmu 0x1187 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2168 0x0400>,
<&apps_smmu 0x1188 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb9 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
iommus = <&apps_smmu 0x2169 0x0400>,
<&apps_smmu 0x1189 0x0420>;
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb10 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1803 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb11 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1804 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb12 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1805 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb13 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "sdsprpc-smd";
iommus = <&apps_smmu 0x0541 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb14 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "sdsprpc-smd";
iommus = <&apps_smmu 0x0542 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb15 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "sdsprpc-smd";
iommus = <&apps_smmu 0x0543 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
shared-cb = <4>;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb16 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x118B 0x0420>,
<&apps_smmu 0x216B 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb17 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x118C 0x0420>,
<&apps_smmu 0x216C 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb18 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x118D 0x0420>,
<&apps_smmu 0x216D 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb19 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x118E 0x0420>,
<&apps_smmu 0x216E 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
};
llcc_pmu: llcc-pmu@9095000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x09095000 0x300>;
reg-names = "lagg-base";
};
llcc_bw_opp_table: llcc-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */
};
ddr_bw_opp_table: ddr-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */
BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
BW_OPP_ENTRY_DDR( 1708, 4, 0x180); /* 6515 MB/s */
BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */
BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */
BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
BW_OPP_ENTRY_DDR( 3196, 4, 0x100); /* 12191 MB/s */
};
qoslat_opp_table: qoslat-opp-table {
compatible = "operating-points-v2";
opp-1 {
opp-hz = /bits/ 64 < 1 >;
};
opp-2 {
opp-hz = /bits/ 64 < 2 >;
};
};
cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
compatible = "qcom,devfreq-icc";
governor = "bw_hwmon";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
compatible = "qcom,bimc-bwmon4";
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_cpu_llcc_bw>;
qcom,count-unit = <0x10000>;
};
cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
compatible = "qcom,devfreq-icc-ddr";
governor = "bw_hwmon";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
compatible = "qcom,bimc-bwmon5";
reg = <0x9091000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_llcc_ddr_bw>;
qcom,count-unit = <0x10000>;
};
cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU0>;
};
cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU1>;
};
cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU2>;
};
cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU3>;
};
cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU4>;
};
cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU5>;
};
cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU6>;
};
cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
};
cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "compute";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
};
snoop_l3_bw: qcom,snoop-l3-bw {
compatible = "qcom,devfreq-icc-l3bw";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
qcom,bus-width = <32>;
governor = "bw_hwmon";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
};
snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 {
compatible = "qcom,bimc-bwmon4";
reg = <0x90b9100 0x300>, <0x90b9000 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&snoop_l3_bw>;
qcom,count-unit = <0x10000>;
};
cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor {
compatible = "qcom,devfreq-icc";
governor = "compute";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
compatible = "qcom,devfreq-qoslat";
governor = "mem_latency";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor {
compatible = "qcom,devfreq-qoslat";
governor = "mem_latency";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
qcom,core-dev-table =
< 300000 300000000 >,
< 403200 403200000 >,
< 499200 499200000 >,
< 691200 614400000 >,
< 806400 710400000 >,
< 998400 806400000 >,
< 1190400 998400000 >,
< 1286400 1094400000 >,
< 1459200 1248000000 >,
< 1728000 1344000000 >,
< 1804800 1440000000 >,
< 1900800 1516800000 >;
};
cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl {
qcom,core-dev-table =
< 300000 300000000 >,
< 787200 614400000 >,
< 1209600 806400000 >,
< 1497600 998400000 >,
< 1689600 1248000000 >,
< 1900800 1344000000 >,
< 2188800 1440000000 >,
< 2400000 1516800000 >;
};
memlat_cpugrp: qcom,memlat-cpugrp {
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3
&CPU4 &CPU5 &CPU6 &CPU7>;
cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0>;
qcom,target-dev = <&cpu0_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU1>;
qcom,target-dev = <&cpu1_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU2>;
qcom,target-dev = <&cpu2_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU3>;
qcom,target-dev = <&cpu3_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&cpu0_cpu_llcc_lat>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 300000 MHZ_TO_MBPS( 150, 16) >,
< 691200 MHZ_TO_MBPS( 300, 16) >,
< 1459200 MHZ_TO_MBPS( 466, 16) >,
< 1900800 MHZ_TO_MBPS( 600, 16) >;
};
cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&cpu0_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 300000 MHZ_TO_MBPS( 200, 4) >,
< 691200 MHZ_TO_MBPS( 451, 4) >,
< 1190400 MHZ_TO_MBPS( 547, 4) >,
< 1459200 MHZ_TO_MBPS( 768, 4) >,
< 1900800 MHZ_TO_MBPS( 1017, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 300000 MHZ_TO_MBPS( 200, 4) >,
< 691200 MHZ_TO_MBPS( 451, 4) >,
< 1190400 MHZ_TO_MBPS( 547, 4) >,
< 1459200 MHZ_TO_MBPS( 768, 4) >,
< 1900800 MHZ_TO_MBPS( 1555, 4) >;
};
};
cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4>;
qcom,target-dev = <&cpu4_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU5>;
qcom,target-dev = <&cpu5_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU6>;
qcom,target-dev = <&cpu6_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu7_l3_computemon: qcom,cpu7-l3-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_latfloor>;
qcom,core-dev-table =
< 1996800 300000000 >,
< 2400000 1516800000 >;
};
cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_cpu_llcc_lat>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 300000 MHZ_TO_MBPS( 150, 16) >,
< 672000 MHZ_TO_MBPS( 300, 16) >,
< 1017600 MHZ_TO_MBPS( 466, 16) >,
< 1305600 MHZ_TO_MBPS( 600, 16) >,
< 1804800 MHZ_TO_MBPS( 806, 16) >,
< 2304000 MHZ_TO_MBPS( 933, 16) >,
< 2400000 MHZ_TO_MBPS( 1000, 16) >;
};
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 300000 MHZ_TO_MBPS( 200, 4) >,
< 672000 MHZ_TO_MBPS( 451, 4) >,
< 902400 MHZ_TO_MBPS( 547, 4) >,
< 1017600 MHZ_TO_MBPS( 768, 4) >,
< 1305600 MHZ_TO_MBPS(1017, 4) >,
< 1593600 MHZ_TO_MBPS(1353, 4) >,
< 1804800 MHZ_TO_MBPS(1555, 4) >,
< 2188800 MHZ_TO_MBPS(1708, 4) >,
< 2400000 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 300000 MHZ_TO_MBPS( 200, 4) >,
< 672000 MHZ_TO_MBPS( 451, 4) >,
< 902400 MHZ_TO_MBPS( 547, 4) >,
< 1017600 MHZ_TO_MBPS( 768, 4) >,
< 1804800 MHZ_TO_MBPS(1555, 4) >,
< 2304000 MHZ_TO_MBPS(2092, 4) >,
< 2400000 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_computemon: qcom,cpu4-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 1804800 MHZ_TO_MBPS( 200, 4) >,
< 2400000 MHZ_TO_MBPS(1017, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 1804800 MHZ_TO_MBPS( 200, 4) >,
< 2400000 MHZ_TO_MBPS(1555, 4) >;
};
};
cpu4_llcc_computemon: qcom,cpu4-llcc-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;
qcom,core-dev-table =
< 1804800 MHZ_TO_MBPS( 150, 16) >,
< 2400000 MHZ_TO_MBPS( 600, 16) >;
};
cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 2304000 MHZ_TO_MBPS( 200, 4) >,
< 2400000 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 2304000 MHZ_TO_MBPS( 200, 4) >,
< 2400000 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_qoslatmon: qcom,cpu4-qoslatmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 300000 1 >,
< 3000000 2 >;
};
cpu7_qoslatmon: qcom,cpu7-qoslatmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 1996800 1 >,
< 2400000 2 >;
};
};
wdog: qcom,wdt@17c10000{
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
};
tsens0:tsens@c222000 {
compatible = "qcom,tsens24xx";
reg = <0x0C222000 0x8>,
<0x0C263000 0x1ff>;
reg-names = "tsens_srot_physical",
"tsens_tm_physical";
interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tsens-upper-lower", "tsens-critical",
"tsens-0C";
#thermal-sensor-cells = <1>;
};
tsens1:tsens@c223000 {
compatible = "qcom,tsens24xx";
reg = <0x0C223000 0x8>,
<0x0C265000 0x1ff>;
reg-names = "tsens_srot_physical",
"tsens_tm_physical";
interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tsens-upper-lower", "tsens-critical",
"tsens-0C";
#thermal-sensor-cells = <1>;
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "mpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
qcom,modem_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
<&glink_slpi>,
<&glink_spss>;
};
};
glink_adsp: adsp {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "adsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_slpi>,
<&glink_modem>;
};
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3>;
};
};
glink_slpi: dsps {
qcom,remote-pid = <3>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "dsps_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "slpi";
qcom,glink-label = "dsps";
qcom,slpi_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,net-id = <2>;
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,slpi_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
<&glink_modem>;
};
};
glink_cdsp: cdsp {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "dsps_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
};
glink_spss: spss {
qcom,remote-pid = <8>;
transport = "spss";
mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "spss_spss";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0x1885008 0x8>,
<0x1885010 0x4>;
reg-names = "qcom,spss-addr",
"qcom,spss-size";
label = "spss";
qcom,glink-label = "spss";
qcom,spss_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>;
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
};
pil_modem: qcom,mss@8a800000 {
compatible = "qcom,pil-tz-generic";
reg = <0x4080000 0x100>;
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mss-supply = <&VDD_MODEM_LEVEL>;
qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,firmware-name = "modem";
memory-region = <&pil_modem_mem>;
qcom,proxy-timeout-ms = <10000>;
qcom,sysmon-id = <0>;
qcom,minidump-id = <3>;
qcom,aux-minidump-ids = <4>;
qcom,ssctl-instance-id = <0x12>;
qcom,pas-id = <4>;
qcom,smem-id = <421>;
qcom,signal-aop;
qcom,complete-ramdump;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "mss-pil";
};
qcom,lpass@17300000 {
compatible = "qcom,pil-tz-generic";
reg = <0x17300000 0x00100>;
vdd_cx-supply = <&VDD_LPI_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
vdd_mx-supply = <&VDD_LPI_MX_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <1>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <423>;
qcom,minidump-id = <5>;
qcom,sysmon-id = <1>;
qcom,ssctl-instance-id = <0x14>;
qcom,firmware-name = "adsp";
memory-region = <&pil_adsp_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
qcom,minidump-as-elf32;
/* Inputs from lpass */
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack";
/* Outputs to lpass */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "adsp-pil";
};
qcom,turing@0x98900000 {
compatible = "qcom,pil-tz-generic";
reg = <0x98900000 0x1400000>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mx-supply = <&VDD_MXC_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <18>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <601>;
qcom,minidump-id = <7>;
qcom,sysmon-id = <7>;
qcom,ssctl-instance-id = <0x17>;
qcom,firmware-name = "cdsp";
memory-region = <&pil_cdsp_mem>;
qcom,complete-ramdump;
qcom,minidump-as-elf32;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
/* Inputs from turing */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
};
qcom,venus@aab0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xaab0000 0x2000>;
vdd-supply = <&video_cc_mvs0c_gdsc>;
qcom,proxy-reg-names = "vdd";
qcom,complete-ramdump;
clocks = <&clock_videocc VIDEO_CC_XO_CLK>,
<&clock_videocc VIDEO_CC_MVS0C_CLK>,
<&clock_videocc VIDEO_CC_AHB_CLK>;
clock-names = "xo", "core", "ahb";
qcom,proxy-clock-names = "xo", "core", "ahb";
qcom,core-freq = <200000000>;
qcom,ahb-freq = <200000000>;
qcom,pas-id = <9>;
interconnect-names = "pil-venus";
interconnects = <&mmss_noc MASTER_VIDEO_P0
&mc_virt SLAVE_EBI1>;
qcom,proxy-timeout-ms = <100>;
qcom,firmware-name = "venus";
memory-region = <&pil_video_mem>;
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
qcom,ipa-platform-type-msm;
qcom,ipa-advertise-sg-support;
qcom,ipa-napi-enable;
};
qcom,ipa_fws {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "ipa_fws";
qcom,pil-force-shutdown;
memory-region = <&pil_ipa_gsi_mem>;
};
ipa_hw: qcom,ipa@1e00000 {
compatible = "qcom,ipa";
mboxes = <&qmp_aop 0>;
reg =
<0x1e00000 0x84000>,
<0x1e04000 0x23000>;
reg-names = "ipa-base", "gsi-base";
interrupts =
<0 654 IRQ_TYPE_LEVEL_HIGH>,
<0 432 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
qcom,ipa-hw-ver = <19>; /* IPA core version = IPAv4.9 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <1>; /* MSM platform */
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
qcom,modem-cfg-emb-pipe-flt;
qcom,ipa-wdi3-over-gsi;
qcom,arm-smmu;
qcom,smmu-fast-map;
qcom,use-64-bit-dma-mask;
qcom,ipa-endp-delay-wa;
qcom,lan-rx-napi;
qcom,tx-napi;
qcom,wan-use-skb-page;
qcom,rmnet-ctl-enable;
qcom,ipa-uc-holb-monitor;
qcom,gsi_wdi_db_polling;
qcom,ipa-holb-monitor-poll-period = <5>;
qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
qcom,ipa-holb-monitor-max-cnt-usb = <10>;
qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
qcom,tx-wrapper-cache-max-size = <400>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&clock_rpmh RPMH_IPA_CLK>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <3>;
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<150000 600000 150000 1804000 0 74000>;
/* SVS */
qcom,svs =
<625000 1200000 625000 3072000 0 150000>;
/* NOMINAL */
qcom,nominal =
<1250000 2400000 1250000 6220800 0 400000>;
/* TURBO */
qcom,turbo =
<2000000 3500000 2000000 7219200 0 400000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
"TURBO";
qcom,throughput-threshold = <600 2500 5000>;
qcom,scaling-exceptions = <>;
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x5C0 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,additional-mapping =
/* modem tables in IMEM */
<0x146BD000 0x146BD000 0x2000>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,ipa-q6-smem-size = <36864>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x5C1 0x0>;
qcom,iommu-dma = "atomic";
dma-coherent;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x5C2 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,iommu-dma = "atomic";
};
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x5C3 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <>;
};
};
qcom,evass@abb0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xabb0000 0x2000>;
status = "ok"
qcom,pas-id = <26>;
qcom,firmware-name = "evass";
memory-region = <&pil_cvp_mem>;
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c100_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c200_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c300_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
c400_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x4>;
};
c500_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x5>;
};
c600_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x6>;
};
c700_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x7>;
};
c0_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x130>;
};
c100_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x131>;
};
c200_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x132>;
};
c300_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x133>;
};
c400_scandump: c400_scandump {
qcom,dump-size = <0x1a4c0>;
qcom,dump-id = <0x134>;
};
c500_scandump: c500_scandump {
qcom,dump-size = <0x1a4c0>;
qcom,dump-id = <0x135>;
};
c600_scandump: c600_scandump {
qcom,dump-size = <0x1a4c0>;
qcom,dump-id = <0x136>;
};
c700_scandump: c700_scandump {
qcom,dump-size = <0x1a4c0>;
qcom,dump-id = <0x137>;
};
cpuss_reg {
qcom,dump-size = <0x30000>;
qcom,dump-id = <0xef>;
};
l1_icache0 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x60>;
};
l1_icache100 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x61>;
};
l1_icache200 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x62>;
};
l1_icache300 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x63>;
};
l1_icache400 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x64>;
};
l1_icache500 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x65>;
};
l1_icache600 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x66>;
};
l1_icache700 {
qcom,dump-size = <0x32100>;
qcom,dump-id = <0x67>;
};
l1_dcache0 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x80>;
};
l1_dcache100 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x81>;
};
l1_dcache200 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x82>;
};
l1_dcache300 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x83>;
};
l1_dcache400 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x84>;
};
l1_dcache500 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x85>;
};
l1_dcache600 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x86>;
};
l1_dcache700 {
qcom,dump-size = <0x12100>;
qcom,dump-id = <0x87>;
};
l1_itlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x24>;
};
l1_itlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x25>;
};
l1_itlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x26>;
};
l1_itlb700 {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x27>;
};
l1_dtlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x44>;
};
l1_dtlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x45>;
};
l1_dtlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x46>;
};
l1_dtlb700 {
qcom,dump-size = <0x3a0>;
qcom,dump-id = <0x47>;
};
l2_cache400 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc4>;
};
l2_cache500 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc5>;
};
l2_cache600 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc6>;
};
l2_cache700 {
qcom,dump-size = <0x120100>;
qcom,dump-id = <0xc7>;
};
l2_tlb0 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x120>;
};
l2_tlb100 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x121>;
};
l2_tlb200 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x122>;
};
l2_tlb300 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x123>;
};
l2_tlb400 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x124>;
};
l2_tlb500 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x125>;
};
l2_tlb600 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x126>;
};
l2_tlb700 {
qcom,dump-size = <0xc100>;
qcom,dump-id = <0x127>;
};
gemnoc {
qcom,dump-size = <0x100000>;
qcom,dump-id = <0x162>;
};
mhm_scan {
qcom,dump-size = <0x20000>;
qcom,dump-id = <0x161>;
};
rpmh {
qcom,dump-size = <0x2000000>;
qcom,dump-id = <0xec>;
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
fcm {
qcom,dump-size = <0x8400>;
qcom,dump-id = <0xee>;
};
etf_swao {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xf1>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etfswao_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x102>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
etf_slpi {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf3>;
};
etfslpi_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x103>;
};
etf_lpass {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf4>;
};
etflpass_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
LLCC_1: llcc_1_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x140>;
};
LLCC_2: llcc_2_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x141>;
};
LLCC_3: llcc_3_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x142>;
};
LLCC_4: llcc_4_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x143>;
};
};
qcom,ssc@5c00000 {
compatible = "qcom,pil-tz-generic";
reg = <0x5c00000 0x4000>;
vdd_cx-supply = <&VDD_LPI_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
vdd_mx-supply = <&VDD_LPI_MX_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <12>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <424>;
qcom,sysmon-id = <3>;
qcom,ssctl-instance-id = <0x16>;
qcom,firmware-name = "slpi";
status = "ok"
memory-region = <&pil_slpi_mem>;
qcom,complete-ramdump;
qcom,signal-aop;
/* Inputs from ssc */
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
<&dsps_smp2p_in 0 0>,
<&dsps_smp2p_in 2 0>,
<&dsps_smp2p_in 1 0>,
<&dsps_smp2p_in 3 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack";
/* Outputs to ssc */
qcom,smem-states = <&dsps_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "slpi-pil";
};
/* PIL spss node - for loading Secure Processor */
qcom,spss@1880000 {
compatible = "qcom,pil-tz-generic";
reg = <0x188101c 0x4>,
<0x1881024 0x4>,
<0x1881028 0x4>,
<0x188103c 0x4>,
<0x1881100 0x4>,
<0x1882014 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
"sp2soc_irq_mask", "rmb_err",
"rmb_general_purpose", "rmb_err_spare2";
interrupts = <0 352 1>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pil-generic-irq-handler;
status = "ok"
qcom,signal-aop;
qcom,complete-ramdump;
qcom,boot-enabled;
qcom,pas-id = <14>;
qcom,proxy-timeout-ms = <10000>;
qcom,firmware-name = "spss";
memory-region = <&pil_spss_mem>;
qcom,spss-scsr-bits = <24 25>;
qcom,extra-size = <4096>;
mboxes = <&qmp_aop 0>;
mbox-names = "spss-pil";
};
qcom,trustedvm@d0800000 {
compatible = "qcom,pil-tz-generic";
status = "ok"
qcom,pas-id = <28>;
qcom,firmware-name = "trustedvm";
memory-region = <&pil_trustedvm_mem>;
};
qcom,guestvm_loader {
compatible = "qcom,guestvm-loader";
image_to_be_loaded = "trustedvm";
qcom,reserved-cpus = <4 5>;
qcom,unisolate-timeout-ms = <8000>;
};
ssc_sensors: qcom,msm-ssc-sensors {
compatible = "qcom,msm-ssc-sensors";
status = "ok"
qcom,firmware-name = "slpi";
};
qcom_tzlog: tz-log@146bf720 {
compatible = "qcom,tz-log";
reg = <0x146bf720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom_qseecom: qseecom@c1700000 {
compatible = "qcom,qseecom";
memory-region = <&qseecom_mem>;
qcom,hlos-num-ce-hw-instances = <1>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,no-clock-support;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
qcom,qsee-reentrancy-support = <2>;
};
qcom,spcom {
compatible = "qcom,spcom";
/* predefined channels, remote side is server */
qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
/* sp2soc rmb shared register physical address and bmsk */
qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
/* soc2sp rmb shared register physical address */
qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
qcom,boot-enabled;
status = "ok"
};
spss_utils: qcom,spss_utils {
compatible = "qcom,spss-utils";
/* spss fuses physical address */
qcom,spss-fuse1-addr = <0x00780204>;
qcom,spss-fuse1-bit = <9>;
qcom,spss-fuse2-addr = <0x00780204>;
qcom,spss-fuse2-bit = <8>;
qcom,spss-fuse3-addr = <0x007801C0>; // IAR_FEATURE_ENABLED fuse
qcom,spss-fuse3-bit = <10>;
qcom,spss-fuse4-addr = <0x00780204>; // IAR_STATE fuse
qcom,spss-fuse4-bit = <25>; // 0x00780204 bits 25-27
qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */
qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */
qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */
qcom,spss-debug-reg-addr = <0x01886020>;
qcom,spss-scsr-regs-addr = <0x01880000>; /* SPU shared register */
qcom,spss-emul-type-reg-addr = <0x01fc8004>;
pil-mem = <&pil_spss_mem>;
qcom,pil-size = <0x0F0000>; // padding to 960 KB
status = "ok"
};
hyp_core_ctl: qcom,hyp-core-ctl {
compatible = "qcom,hyp-core-ctl";
status = "ok"
};
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupt-parent = <&pdc>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x088E0000 0x2000>,
<0x088E2000 0x1000>;
reg-names = "eud_base", "eud_mode_mgr2";
qcom,secure-eud-en;
status = "ok"
};
qcom_rng: qrng@10d3000 {
compatible = "qcom,msm-rng";
reg = <0x10d3000 0x1000>;
qcom,no-qrng-config;
interconnect-names = "data_path";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_HWKM>;
clock-names = "km_clk_src";
clocks = <&clock_rpmh RPMH_HWKM_CLK>;
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <3>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0586 0x0011>,
<&apps_smmu 0x0596 0x0011>;
qcom,iommu-dma = "atomic";
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x592 0>,
<&apps_smmu 0x598 0>,
<&apps_smmu 0x599 0>,
<&apps_smmu 0x59F 0>;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x593 0>,
<&apps_smmu 0x59C 0>,
<&apps_smmu 0x59D 0>,
<&apps_smmu 0x59E 0>;
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
qcom,secure-context-bank;
};
};
qcom_crypto: qcrypto@1de0000 {
compatible = "qcom,qcrypto";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,bam-ee = <0>;
qcom,ce-hw-shared;
qcom,clk-mgmt-sus-res;
qcom,use-sw-aes-cbc-ecb-ctr-algo;
qcom,use-sw-aes-xts-algo;
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
qcom,use-sw-aead-algo;
qcom,use-sw-hmac-algo;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0584 0x0011>,
<&apps_smmu 0x0594 0x0011>;
qcom,iommu-dma = "atomic";
};
wlan: qcom,cnss-qca6490@b0000000 {
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>,
<0xb2e5510 0x690>;
reg-names = "smmu_iova_ipa", "tcs_cmd";
wlan-en-gpio = <&tlmm 64 0>;
qcom,bt-en-gpio = <&tlmm 65 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x420000>;
qcom,wlan-cbc-enabled;
/* RPMH_PDC_WLAN_RF_TCS<6>_CMD<2> offset */
qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>;
use-pm-domain;
cnss-enable-self-recovery;
vdd-wlan-aon-supply = <&S2E>;
qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
vdd-wlan-dig-supply = <&S11B>;
qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
vdd-wlan-io-supply = <&S10B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-rfa1-supply = <&S1C>;
qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>;
vdd-wlan-rfa2-supply = <&S12B>;
qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
wlan-ant-switch-supply = <&L7E>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
interconnects =
<&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <7>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<2250 390000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<7500 390000>,
/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<30000 790000>,
/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<100000 790000>,
/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
<175000 1600000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
* ddr: 547.2 MHz
*/
<7500 390000>,
/** ICC Path 2 **/
<0 0>,
<2250 1804800>,
<7500 1804800>,
<30000 1804800>,
<100000 1804800>,
<175000 6220800>,
<7500 2188800>;
mhi,max-channels = <30>;
mhi,timeout = <10000>;
mhi,buffer-len = <0x8000>;
mhi,m2-no-db-access;
mhi_channels {
#address-cells = <1>;
#size-cells = <0>;
mhi_chan@0 {
reg = <0>;
label = "LOOPBACK";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <1>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@1 {
reg = <1>;
label = "LOOPBACK";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <2>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@4 {
reg = <4>;
label = "DIAG";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <1>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@5 {
reg = <5>;
label = "DIAG";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <2>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@20 {
reg = <20>;
label = "IPCR";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <1>;
mhi,data-type = <1>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
mhi,auto-start;
};
mhi_chan@21 {
reg = <21>;
label = "IPCR";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <2>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
mhi,auto-queue;
mhi,auto-start;
};
};
mhi_events {
mhi_event@0 {
mhi,num-elements = <32>;
mhi,intmod = <0>;
mhi,msi = <1>;
mhi,priority = <0>;
mhi,brstmode = <2>;
mhi,data-type = <1>;
};
mhi_event@1 {
mhi,num-elements = <256>;
mhi,intmod = <0>;
mhi,msi = <2>;
mhi,priority = <1>;
mhi,brstmode = <2>;
};
mhi_event@2 {
mhi,num-elements = <32>;
mhi,intmod = <0>;
mhi,msi = <0>;
mhi,priority = <2>;
mhi,brstmode = <2>;
mhi,data-type = <3>;
};
};
mhi_devices {
mhi_qrtr {
mhi,chan = "IPCR";
qcom,net-id = <0>;
qcom,low-latency;
};
};
};
qcom,pmic_glink {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
qcom,subsys-name = "adsp";
qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
battery_charger: qcom,battery_charger {
compatible = "qcom,battery-charger";
};
qcom,ucsi {
compatible = "qcom,ucsi-glink";
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
altmode: qcom,altmode {
compatible = "qcom,altmode-glink";
#altmode-cells = <1>;
};
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pm8350b-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
qcom,can-sleep;
};
};
/* Secondary (QUP) SPMI bus */
spmi@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
qcom,smb1396-debug@b {
compatible = "qcom,spmi-pmic";
reg = <0xb SPMI_USID>;
qcom,can-sleep;
};
qcom,smb1396-debug@c {
compatible = "qcom,spmi-pmic";
reg = <0xc SPMI_USID>;
qcom,can-sleep;
};
smb1398_debug: qcom,smb1398-debug@d {
compatible = "qcom,spmi-pmic";
reg = <0xd SPMI_USID>;
qcom,can-sleep;
status = "disabled";
};
};
};
};
bluetooth: bt_qca6490 {
compatible = "qcom,qca6490";
reg = <0xb2e5510 0x690>;
reg-names = "tcs_cmd";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_sleep>;
/* offset=(0xC8*6) + (0x10*2) */
qcom,tcs_offset_ipa = <0x4D0>;
qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */
qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 153 0>; /* SW_CTRL */
qcom,bt-vdd-aon-supply = <&S11B>;
qcom,bt-vdd-dig-supply = <&S11B>;
qcom,bt-vdd-rfa1-supply = <&S1C>;
qcom,bt-vdd-rfa2-supply = <&S12B>;
qcom,bt-vdd-asd-supply = <&L7E>;
qcom,bt-vdd-aon-config = <950000 950000 0 1>;
qcom,bt-vdd-dig-config = <950000 950000 0 1>;
qcom,bt-vdd-rfa1-config = <1880000 1880000 0 1>;
qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>;
qcom,bt-vdd-asd-config = <2800000 2800000 0 1>;
};
wil6210: qcom,wil6210 {
compatible = "qcom,wil6210";
qcom,pcie-parent = <&pcie1>;
qcom,wigig-en = <&tlmm 47 0>;
pinctrl-names = "default";
pinctrl-0 = <&wil6210_refclk_en_pin>;
qcom,11ad-bus-bw,name = "wil6210";
qcom,11ad-bus-bw,num-cases = <3>;
qcom,11ad-bus-bw,num-paths = <1>;
qcom,11ad-bus-bw,vectors-KBps =
<100 512 0 0>,
<100 512 600000 800000>, /* ~4.6Gbps (MCS12) */
<100 512 1300000 1300000>; /* ~10.1Gbps */
qcom,use-ext-supply;
vdd-s1c-supply = <&S1C>;
qcom,use-ext-clocks;
clocks = <&clock_rpmh RPMH_RF_CLK5>;
clock-names = "rf_clk";
qcom,keep-radio-on-during-sleep;
qcom,use-ap-power-save;
status = "disabled";
};
qfprom: qfprom@784000 {
compatible = "qcom,qfprom";
reg = <0x784000 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
gpu_speed_bin: gpu_speed_bin@17b {
reg = <0x17b 0x1>;
bits = <5 3>;
};
};
};
#include "ipcc-test.dtsi"
#include "lahaina-regulators.dtsi"
#include "lahaina-pinctrl.dtsi"
#include "lahaina-smp2p.dtsi"
#include "lahaina-ion.dtsi"
#include "msm-arm-smmu-lahaina.dtsi"
#include "lahaina-usb.dtsi"
#include "lahaina-coresight.dtsi"
#include "lahaina-pm.dtsi"
#include "lahaina-qupv3.dtsi"
#include "lahaina-audio.dtsi"
#include "lahaina-vidc.dtsi"
#include "lahaina-cvp.dtsi"
#include "lahaina-pcie.dtsi"
#include "msm-qvr-external.dtsi"
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci: cnss_pci {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group>;
memory-region = <&cnss_wlan_mem>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci_iommu_group: cnss_pci_iommu_group {
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
"non-fatal";
};
};
};
&pcie1_rp {
#address-cells = <5>;
#size-cells = <0>;
wil6210_pci: wil6210_pci {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&wil6210_pci_iommu_group>;
#address-cells = <1>;
#size-cells = <1>;
wil6210_pci_iommu_group: wil6210_pci_iommu_group {
reg = <0 0>;
qcom,iommu-dma-addr-pool = <0x60000000 0xa0000000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
};
};
};
#include "lahaina-gpu.dtsi"
#include "display/lahaina-sde.dtsi"
#include "lahaina-thermal.dtsi"
&qupv3_se18_4uart {
status = "ok"
};
&qupv3_se13_i2c {
status = "ok"
nq@64 {
compatible = "rtc6226";
reg = <0x64>;
fmint-gpio = <&tlmm 50 0>;
vdd-supply = <&L7E>;
rtc6226,vdd-supply-voltage = <2800000 2800000>;
vio-supply = <&S10B>;
rtc6226,vio-supply-voltage = <1800000 1800000 >;
};
};
#include "camera/lahaina-camera.dtsi"
#include "msm-rdbg.dtsi"
Reference in a new issue View git blame Copy permalink