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| Filename | Latest commit message | Latest commit date |
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Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Mohit KUMAR <[email protected]> |
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| .. | ||
| bindings | ||
| 00-INDEX | ||
| booting-without-of.txt | ||
| usage-model.txt | ||