mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-10 21:02:03 -05:00
09cb182376
QUP core clock is shared among all the SE drivers, during earlybootup if any SE driver turn off the clock before real console gets probe, the device will crash because of unclocked access by earlycon. In order to fix this move the console device definition up in DT file this ensures that console probe is called before other SE drivers. Change-Id: I341940fd56890b9c6b316fd767eb79d384948efd
325 lines
9.6 KiB
Devicetree
325 lines
9.6 KiB
Devicetree
#include <dt-bindings/interconnect/qcom,holi.h>
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&soc {
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/* QUPv3 SE Instances
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* Qup0 0: SE 0: I2C, SPI
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* Qup0 1: SE 1: HSUART
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* Qup0 2: SE 2: I2C, SPI
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* Qup0 3: SE 3: Not bolled out
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* Qup0 4: SE 4: Not bolled out
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* Qup0 5: SE 5: Not bolled out
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* Qup1 0: SE 6: I2C, SPI
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* Qup1 1: SE 7: I2C
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* Qup1 2: SE 8: I2C
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* Qup1 3: SE 9: DEBUG UART
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* Qup1 4: SE 10: I2C
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* Qup1 5: SE 11: Not bolled out
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*/
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x4ac0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
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<MASTER_QUP_0 SLAVE_EBI>;
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qcom,vote-for-bw;
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iommus = <&apps_smmu 0x0003 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok"
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};
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@4a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x4a00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x0016 0x0>;
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qcom,max-num-gpii = <10>;
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interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x1f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok"
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};
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/* Debug UART Instance */
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qupv3_se9_2uart: qcom,qup_uart@4c8c000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x4c8c000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se9_2uart_active>;
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pinctrl-1 = <&qupv3_se9_2uart_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se0_i2c: i2c@4a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se0_spi: spi@4a80000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* HS UART Instance */
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qupv3_se1_4uart: qcom,qup_uart@4a84000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x4a84000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 64 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qupv3_se1_default_cts>,
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<&qupv3_se1_default_rtsrx>, <&qupv3_se1_default_tx>;
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pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
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<&qupv3_se1_tx>;
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pinctrl-2 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
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<&qupv3_se1_tx>;
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qcom,wakeup-byte = <0xFD>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@4a88000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_spi: spi@4a88000 {
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compatible = "qcom,spi-geni";
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reg = <0x4a88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@4cc0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x4cc0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_CORE_1 SLAVE_QUP_CORE_1>,
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<MASTER_QUP_1 SLAVE_EBI>;
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qcom,vote-for-bw;
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iommus = <&apps_smmu 0x00c3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok"
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};
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/* GPI Instance */
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gpi_dma1: qcom,gpi-dma@4c00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x4c00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x00d6 0x0>;
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qcom,max-num-gpii = <10>;
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interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x1f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok"
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};
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qupv3_se6_i2c: i2c@4c80000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4c80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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dmas = <&gpi_dma1 0 0 3 64 0>,
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<&gpi_dma1 1 0 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se6_spi: spi@4c80000 {
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compatible = "qcom,spi-geni";
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reg = <0x4c80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_spi_active>;
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pinctrl-1 = <&qupv3_se6_spi_sleep>;
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dmas = <&gpi_dma1 0 0 1 64 0>,
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<&gpi_dma1 1 0 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@4c84000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4c84000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_i2c_active>;
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pinctrl-1 = <&qupv3_se7_i2c_sleep>;
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dmas = <&gpi_dma1 0 1 3 64 0>,
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<&gpi_dma1 1 1 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se8_i2c: i2c@4c88000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4c88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_i2c_active>;
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pinctrl-1 = <&qupv3_se8_i2c_sleep>;
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dmas = <&gpi_dma1 0 2 3 64 0>,
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<&gpi_dma1 1 2 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se10_i2c: i2c@4c90000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4c90000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_i2c_active>;
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pinctrl-1 = <&qupv3_se10_i2c_sleep>;
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dmas = <&gpi_dma1 0 4 3 64 0>,
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<&gpi_dma1 1 4 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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};
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