mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-09 04:12:08 -05:00
749 lines
15 KiB
Devicetree
749 lines
15 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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/ {
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model = "Qualcomm Technologies, Inc. SM8150";
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compatible = "qcom,sm8150";
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qcom,msm-name = "SM8150 V1";
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qcom,msm-id = <339 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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serial0 = &uart2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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L2_TLB_0: l2-tlb {
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qcom,dump-size = <0x5000>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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L2_TLB_100: l2-tlb {
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qcom,dump-size = <0x5000>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_200: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_200: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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L2_TLB_200: l2-tlb {
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qcom,dump-size = <0x5000>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_300: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_300: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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L2_TLB_300: l2-tlb {
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qcom,dump-size = <0x5000>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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qcom,dump-size = <0x88000>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x11000>;
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_ITLB_400: l1-itlb {
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qcom,dump-size = <0x300>;
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};
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L1_DTLB_400: l1-dtlb {
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qcom,dump-size = <0x480>;
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};
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L2_TLB_400: l2-tlb {
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qcom,dump-size = <0x7800>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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qcom,dump-size = <0x88000>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x11000>;
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_ITLB_500: l1-itlb {
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qcom,dump-size = <0x300>;
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};
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L1_DTLB_500: l1-dtlb {
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qcom,dump-size = <0x480>;
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};
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L2_TLB_500: l2-tlb {
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qcom,dump-size = <0x7800>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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qcom,dump-size = <0x88000>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x11000>;
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_ITLB_600: l1-itlb {
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qcom,dump-size = <0x300>;
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};
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L1_DTLB_600: l1-dtlb {
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qcom,dump-size = <0x480>;
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};
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L2_TLB_600: l2-tlb {
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qcom,dump-size = <0x7800>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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qcom,dump-size = <0x110000>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x11000>;
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_ITLB_700: l1-itlb {
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qcom,dump-size = <0x300>;
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};
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L1_DTLB_700: l1-dtlb {
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qcom,dump-size = <0x480>;
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};
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L2_TLB_700: l2-tlb {
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qcom,dump-size = <0x7800>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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chosen { };
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soc: soc { };
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firmware: firmware { };
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp_mem {
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no-map;
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_mem: xbl_mem {
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no-map;
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reg = <0x0 0x85e00000 0x0 0x100000>;
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};
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aop_mem: memory@85f00000 {
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reg = <0x0 0x85f00000 0x0 0x20000>;
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no-map;
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};
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aop_cmd_db: memory@85f20000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x85f20000 0x0 0x20000>;
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no-map;
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};
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smem_region: smem {
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no-map;
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reg = <0x0 0x86000000 0x0 0x200000>;
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};
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removed_regions: removed_regions {
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no-map;
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reg = <0x0 0x86200000 0x0 0x5500000>;
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};
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pil_camera_mem: camera_region {
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no-map;
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reg = <0x0 0x8b700000 0x0 0x500000>;
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};
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pil_wlan_fw_mem: pil_wlan_fw_region {
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no-map;
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reg = <0x0 0x8bc00000 0x0 0x180000>;
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};
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pil_npu_mem: pil_npu_region {
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no-map;
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reg = <0x0 0x8bd80000 0x0 0x80000>;
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};
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pil_adsp_mem: pil_adsp_region {
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no-map;
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reg = <0x0 0x8be00000 0x0 0x1a00000>;
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};
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pil_modem_mem: modem_region {
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no-map;
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reg = <0x0 0x8d800000 0x0 0x9600000>;
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};
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pil_video_mem: pil_video_region {
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no-map;
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reg = <0x0 0x96e00000 0x0 0x500000>;
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};
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pil_slpi_mem: pil_slpi_region {
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no-map;
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reg = <0x0 0x97300000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: pil_ipa_fw_region {
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no-map;
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reg = <0x0 0x98700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: pil_ipa_gsi_region {
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no-map;
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reg = <0x0 0x98710000 0x0 0x5000>;
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};
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pil_gpu_mem: pil_gpu_region {
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no-map;
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reg = <0x0 0x98715000 0x0 0x2000>;
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};
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pil_spss_mem: pil_spss_region {
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no-map;
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reg = <0x0 0x98800000 0x0 0x100000>;
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};
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pil_cdsp_mem: cdsp_regions {
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no-map;
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reg = <0x0 0x98900000 0x0 0x1400000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0x9e400000 0x0 0x1400000>;
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};
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cdsp_sec_mem: cdsp_sec_regions {
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no-map;
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reg = <0x0 0xa4c00000 0x0 0x3c00000>;
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};
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cont_splash_memory: cont_splash_region {
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reg = <0x0 0x9c000000 0x0 0x2400000>;
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label = "cont_splash_region";
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};
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disp_rdump_memory: disp_rdump_region {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "disp_rdump_region";
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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cdsp_mem: cdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x800000>;
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};
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secure_display_memory: secure_display_region { /* Secure UI */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xA000000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x2400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2800000>;
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linux,cma-default;
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};
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};
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vendor: vendor {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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};
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qcom-secure-buffer {
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compatible = "qcom,secure-buffer";
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32764>;
|
|
clock-output-names = "sleep_clk";
|
|
};
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
|
interrupts = <1 9 4>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sm8150-pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
timer@0x17c20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c20000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@0x17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <0 8 0x4>,
|
|
<0 6 0x4>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <0 9 0x4>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <0 10 0x4>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <0 11 0x4>;
|
|
reg = <0x17c26000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <0 12 0x4>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <0 13 0x4>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <0 14 0x4>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>;
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8150-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board>;
|
|
status = "okay";
|
|
};
|
|
|
|
system_pm {
|
|
compatible = "qcom,system-pm";
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-config = <SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<ACTIVE_TCS 2>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,gcc-sm8150";
|
|
reg = <0x00100000 0x1f0000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
clock-names = "bi_tcxo",
|
|
"sleep_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>;
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x00ac0000 0x6000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc 123>,
|
|
<&gcc 124>;
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "ok"
|
|
|
|
|
|
uart2: serial@a90000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0x0 0x00a90000 0x0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc 105>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "ok"
|
|
};
|
|
};
|
|
};
|
|
|
|
&firmware {
|
|
scm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
};
|
|
|
|
#include "sm8150-ion.dtsi"
|
|
#include "sm8150-pinctrl.dtsi"
|
|
#include "sm8150-regulator.dtsi"
|
|
#include "sm8150-pm.dtsi"
|
|
#include "sm8150-slpi-pinctrl.dtsi"
|