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| Filename | Latest commit message | Latest commit date |
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Check against the max clk_type and clk_state enumerations before to validate the type and state of DSI clocks to avoid Control Flow Integrity issues. Change-Id: Id53465c2b12debb1b356c0c91064eb017c2ca30d Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org> |
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