mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
bc335e4782
Added delay for AQR113 PHY to be in ready state after PHY reset. Change-Id: I90003b155e4567c2a9bed6539f70ec4f7f99b465
132 lines
2.9 KiB
Devicetree
132 lines
2.9 KiB
Devicetree
#include "sdxlemur-mtp-mbb.dtsi"
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&soc {
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qps615_vreg: qps615_vreg {
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compatible = "regulator-fixed";
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regulator-name = "qps615_vreg";
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gpio = <&tlmm 107 GPIO_ACTIVE_HIGH>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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enable-active-high;
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regulator-enable-ramp-delay = <4300>;
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};
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aqr_vreg: aqr_vreg {
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compatible = "regulator-fixed";
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regulator-name = "aqr_vreg";
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gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>;
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vin-supply = <&qps615_vreg>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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enable-active-high;
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regulator-enable-ramp-delay = <10000>;
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};
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ioss_qps615_rx: qps615_rx@eth {
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qcom,dir-rx;
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qcom,rx-filter-ip;
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qcom,ring-size = <128>;
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qcom,buff-size = <2048>;
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qcom,mod-count-min = <64>;
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qcom,mod-count-max = <64>;
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qcom,mod-usecs-min = <30>;
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qcom,mod-usecs-max = <60>;
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};
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ioss_qps615_tx: qps615_tx@eth {
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qcom,dir-tx;
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qcom,ring-size = <512>;
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qcom,buff-size = <2048>;
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qcom,mod-count-min = <64>;
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qcom,mod-count-max = <64>;
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qcom,mod-usecs-min = <30>;
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qcom,mod-usecs-max = <60>;
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};
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};
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&i2c_3 {
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pcie_i2c_ctrl: pcie_i2c_ctrl {
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compatible = "qcom,pcie0-i2c-ntn3";
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reg = <0x77>;
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gpio-config-reg = <0x801208>;
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ep-reset-reg = <0x801210>;
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ep-reset-gpio-mask = <0x9>;
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dump-regs = <0x801330 0x801350 0x801370>;
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};
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};
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&pcie0 {
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pcie-i2c-phandle = <&i2c_3>;
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qcom,filtered-bdfs = <0x02080000>;
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vreg-3p3-supply = <&qps615_vreg>;
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iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
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<0x100 &apps_smmu 0x0201 0x1>,
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<0x210 &apps_smmu 0x0202 0x1>,
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<0x218 &apps_smmu 0x0203 0x1>,
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<0x300 &apps_smmu 0x0208 0x1>,
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<0x400 &apps_smmu 0x020c 0x1>,
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<0x401 &apps_smmu 0x020e 0x1>;
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};
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&pcie0_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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/* BDF 1.0.0 */
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pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 {
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reg = <0 0 0 0 0>;
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/* BDF 2.1.0 */
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pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 {
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reg = <0x800 0x0 0x0 0x0 0x0>;
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};
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/* BDF 2.2.0 */
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pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 {
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reg = <0x1000 0x0 0x0 0x0 0x0>;
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};
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/* BDF 2.3.0 */
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pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 {
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reg = <0x1800 0x0 0x0 0x0 0x0>;
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qps615_eth0,qps615_eth0@pcie0_rp {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "qcom,ioss-v2-device";
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qcom,ioss = <&ioss>;
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qcom,ioss_instance = <0>;
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qcom,ioss_channels =
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<&ioss_qps615_rx>,
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<&ioss_qps615_tx>;
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/* ipa shares this group */
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qcom,iommu-group = <&ipa_eth_group1>;
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phy-supply = <&aqr_vreg>;
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qcom,phy-rst-delay-us = <221000>;
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interrupts-extended = <&tlmm 103 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "wol_irq";
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pinctrl-names = "default";
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pinctrl-0 = <&aqr_intn_wol_sig>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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/* BDF 5.0.0 */
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pcie0_bus5_dev0_fn0: pcie0_ntn3_eth0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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qcom,iommu-group = <ð_pci_iommu_group>;
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eth_pci_iommu_group: eth_pci_iommu_group {
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qcom,iommu-dma = "atomic";
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};
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};
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};
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};
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};
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