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eb919ee4dc
Secure CP control register always assume that it contains 7 bit mask for each PHY. But this register format is different based on target. Update secure CP control bitmask generation logic for each PHY index based on phy_version. So we have below 3 combinations to handle at SW. 1.Old Titan Targets : 7 bits for each PHY. 2.PHY 1_2_1 : for 4 pHYS 7 bits and for remaining 2 PHYs 8 bits are reserved. 3.Mimas (PHY 2_0_1): 8 bits for each PHY. CRs-Fixed: 2624698 Change-Id: Iac4c3c718fc96a51592e07b45458fb045c52366d Signed-off-by: Anil Kumar Kanakanti <akanakan@codeaurora.org> |
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