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Filename Latest commit message Latest commit date
Yuanfang Zhang ecc88751ca ARM: dts: msm: Correct cache and TLB dump size on holi
Current size in dump table is not sufficient as cpu dump lib. so
correct cache and TLB dump size on holi.

Change-Id: I4af84275b25acc1587e7f05edea560862ee5a130
2020-08-24 13:55:00 +08:00
bindings Merge "ARM: dts: msm: Remove unused bite irq from msm watchdog for Shima" 2020-08-21 18:26:13 -07:00
qcom ARM: dts: msm: Correct cache and TLB dump size on holi 2020-08-24 13:55:00 +08:00
Makefile ARM: dts: vendor: Add an initial Makefile to the vendor 2019-06-04 16:50:48 -07:00