Repository files (latest commit first)

Filename	Latest commit message	Latest commit date
Chen-Yu Tsai f0152c58c6 phy: sun4i-usb: Support secondary clock for HSIC PHY ... On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires two clocks instead of one. On all Allwinner SoCs that share the common USB PHY design supported by the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there is at most one HSIC PHY, typically the last. In this patch we take advantage of these known constraints and store an index in the compatible-string-related config structure describing which PHY is HSIC, needing the extra hsic_12M clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>		2017-08-22 10:11:17 +05:30
..
allwinner	phy: sun4i-usb: Support secondary clock for HSIC PHY	2017-08-22 10:11:17 +05:30
amlogic
broadcom	phy: bcm-ns-usb3: add MDIO driver using proper bus layer	2017-06-16 13:22:26 +05:30
hisilicon
marvell
mediatek	phy: phy-mt65xx-usb3: add mediatek directory and rename file	2017-08-20 13:59:51 +05:30
motorola	phy: cpcap-usb: Fix missing return statement	2017-06-16 11:40:21 +05:30
qualcomm	phy: qcom-qmp: Fix failure path in phy_init functions	2017-08-20 13:59:46 +05:30
ralink	phy: ralink-usb: add driver for Mediatek/Ralink	2017-08-20 14:02:23 +05:30
renesas	phy: rcar-gen3-usb3: add support for R-Car Gen3 USB 3.0 PHY	2017-06-07 17:55:13 +05:30
rockchip	phy: rockchip-inno-usb2: add support of usb2-phy for rk3228 SoCs	2017-06-06 14:50:25 +05:30
samsung	phy: samsung: use of_device_get_match_data()	2017-08-20 13:59:52 +05:30
st
tegra
ti	phy: ti-pipe3: Use TRM recommended settings for SATA DPLL	2017-08-20 13:59:47 +05:30
Kconfig	phy: ralink-usb: add driver for Mediatek/Ralink	2017-08-20 14:02:23 +05:30
Makefile	phy: ralink-usb: add driver for Mediatek/Ralink	2017-08-20 14:02:23 +05:30
phy-core.c
phy-lpc18xx-usb-otg.c
phy-pistachio-usb.c
phy-xgene.c