mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
1139a0b43c
Add the "qcom,iommu-dma-addr-pool" property for SA8155 target. Change-Id: Id2e02b83d9b376bc53c9265ac2b3975ebabf474d
113 lines
3.2 KiB
Devicetree
113 lines
3.2 KiB
Devicetree
#include <dt-bindings/interconnect/qcom,sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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&soc {
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/* QUPv3 SSC Instance */
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qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x26c0000 0x6000>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_SENSORS_AHB SLAVE_EBI1>;
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iommus = <&apps_smmu 0x4e3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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status = "disabled";
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};
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/* I2C*/
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qupv3_se20_i2c: i2c@2680000 {
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compatible = "qcom,i2c-geni";
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reg = <0x2680000 0x4000>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_SE0_CLK>,
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<&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se20_i2c_active>;
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pinctrl-1 = <&qupv3_se20_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_3>;
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qcom,disable-dma;
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status = "disabled";
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};
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qupv3_se21_i2c: i2c@2684000 {
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compatible = "qcom,i2c-geni";
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reg = <0x2684000 0x4000>;
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_SE1_CLK>,
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<&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se21_i2c_active>;
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pinctrl-1 = <&qupv3_se21_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_3>;
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qcom,disable-dma;
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status = "disabled";
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};
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qupv3_se22_i2c: i2c@2688000 {
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compatible = "qcom,i2c-geni";
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reg = <0x2688000 0x4000>;
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_SE2_CLK>,
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<&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se22_i2c_active>;
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pinctrl-1 = <&qupv3_se22_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_3>;
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qcom,disable-dma;
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status = "disabled";
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};
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/* SPI */
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qupv3_se21_spi: spi@2684000 {
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compatible = "qcom,spi-geni";
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reg = <0x2684000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_SE1_CLK>,
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<&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se21_spi_active>;
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pinctrl-1 = <&qupv3_se21_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_3>;
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qcom,disable-dma;
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status = "disabled";
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};
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qupv3_se22_spi: spi@2688000 {
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compatible = "qcom,spi-geni";
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reg = <0x2688000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_SE2_CLK>,
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<&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se22_spi_active>;
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pinctrl-1 = <&qupv3_se22_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_3>;
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qcom,disable-dma;
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status = "disabled";
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};
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};
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