mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
6b19d22b6d
This will set the PCIe Wr halt window size to 1GB and disables BDF halt for sdxlemur for PINE attach. In sdxlemur for PINE attaches observed throughput degradation because of PCIe latencies, this is due to PCIe write halt window of 1MB and BDF halt feature enable. So, disabled BDF halt feature and increased PCIe Wr halt window size to 1GB for sdxlemur. Change-Id: I604fcc646a64cddb9502f31c7c357ddc476f741f
66 lines
1.1 KiB
Devicetree
66 lines
1.1 KiB
Devicetree
|
|
#include "sdxlemur-qcn9000.dtsi"
|
|
|
|
&soc {
|
|
pine_vreg: pine_vreg {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "pine_vreg";
|
|
gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
enable-active-high;
|
|
regulator-enable-ramp-delay = <200000>;
|
|
};
|
|
};
|
|
|
|
&qps615_vreg {
|
|
vin-supply = <&pine_vreg>;
|
|
};
|
|
|
|
&pcie0 {
|
|
qcom,no-l0s-supported;
|
|
qcom,no-l1-supported;
|
|
qcom,no-l1ss-supported;
|
|
qcom,no-aux-clk-sync;
|
|
qcom,bdf-halt-dis;
|
|
qcom,wr-halt-size = <0x1e>;
|
|
};
|
|
|
|
&pcie0_bus2_dev1_fn0 {
|
|
cnss_pci1: cnss_pci1 {
|
|
reg = <0 0 0 0 0>;
|
|
qcom,iommu-group = <&qcn9000_pci_iommu_group_0>;
|
|
memory-region = <&qcn9000_0_mem>;
|
|
qrtr_instance_id = <0x20>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&pcie_i2c_ctrl {
|
|
ep_reset_postlinkup;
|
|
reg_update = <0x82c030 0x1
|
|
0x828000 0x3
|
|
0x82bd00 0x8
|
|
0x82c030 0x2
|
|
0x828000 0x3
|
|
0x82bd00 0x8
|
|
0x82c030 0x8
|
|
0x828000 0x1
|
|
0x82bd00 0x8
|
|
0x82c01c 0x10
|
|
0x82c030 0xf
|
|
0x828000 0xf
|
|
0x82b268 0x2>;
|
|
};
|
|
|
|
&wifi0 {
|
|
/* QCN9000 6G */
|
|
board_id = <0xa4>;
|
|
status = "ok"
|
|
};
|
|
|
|
&qcn9000_0_mem {
|
|
status = "ok"
|
|
};
|