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Filename	Latest commit message	Latest commit date
Eugen Hristev b1b8034953 mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R ... [ Upstream commit 5987e6ded29d52e42fc7b06aa575c60a25eee38e ] In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R register. This can lead to accidental erase of certain bits in this register. Avoid this by doing a read-modify-write operation. Fixes: d0918764c1 ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Karl Olsen <karl@micro-technic.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20220630090926.15061-1-eugen.hristev@microchip.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-08-25 11:17:55 +02:00
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core	mmc: block: Fix CQE recovery reset success	2022-06-14 18:12:02 +02:00
host	mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R	2022-08-25 11:17:55 +02:00
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