mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
06b4953933
Add MHI register space information for PCIe so feature such as displaying ASPM stats is possible on SM8150. Change-Id: Ic16e20be3224ba2cdff337e72d9907b6bbbb2d1e
726 lines
13 KiB
Devicetree
726 lines
13 KiB
Devicetree
#include "sm8150.dtsi"
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. SM8150 V2";
|
|
qcom,msm-name = "SM8150 V2";
|
|
qcom,msm-id = <339 0x20000>;
|
|
};
|
|
|
|
/* Remove smmu nodes specific to SM8150 */
|
|
/delete-node/ &apps_smmu;
|
|
/delete-node/ &kgsl_smmu;
|
|
|
|
&spss_utils {
|
|
qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
|
|
qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
|
|
qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
|
|
};
|
|
|
|
&gcc {
|
|
compatible = "qcom,sm8150-gcc-v2", "syscon";
|
|
};
|
|
|
|
&camcc {
|
|
compatible = "qcom,sm8150-camcc-v2", "syscon";
|
|
};
|
|
|
|
&dispcc {
|
|
compatible = "qcom,sm8150-dispcc-v2", "syscon";
|
|
};
|
|
|
|
&videocc {
|
|
compatible = "qcom,sm8150-videocc-v2", "syscon";
|
|
};
|
|
|
|
&npucc {
|
|
compatible = "qcom,sm8150-npucc-v2", "syscon";
|
|
};
|
|
|
|
&scc {
|
|
compatible = "qcom,sm8150-scc-v2", "syscon";
|
|
};
|
|
|
|
#include "msm-arm-smmu-sm8150-v2.dtsi"
|
|
|
|
&pcie0 {
|
|
reg = <0x1c00000 0x4000>,
|
|
<0x1c06000 0x1000>,
|
|
<0x60000000 0xf1d>,
|
|
<0x60000f20 0xa8>,
|
|
<0x60001000 0x1000>,
|
|
<0x60100000 0x100000>,
|
|
<0x60200000 0x100000>,
|
|
<0x60300000 0x3d00000>,
|
|
<0x01c03000 0x1000>;
|
|
|
|
qcom,pcie-phy-ver = <2110>;
|
|
|
|
qcom,phy-sequence = <0x0840 0x03 0x0
|
|
0x0094 0x08 0x0
|
|
0x0154 0x34 0x0
|
|
0x016c 0x08 0x0
|
|
0x0058 0x0f 0x0
|
|
0x00a4 0x42 0x0
|
|
0x0110 0x24 0x0
|
|
0x011c 0x03 0x0
|
|
0x0118 0xb4 0x0
|
|
0x010c 0x02 0x0
|
|
0x01bc 0x11 0x0
|
|
0x00bc 0x82 0x0
|
|
0x00d4 0x03 0x0
|
|
0x00d0 0x55 0x0
|
|
0x00cc 0x55 0x0
|
|
0x00b0 0x1a 0x0
|
|
0x00ac 0x0a 0x0
|
|
0x00c4 0x68 0x0
|
|
0x00e0 0x02 0x0
|
|
0x00dc 0xaa 0x0
|
|
0x00d8 0xab 0x0
|
|
0x00b8 0x34 0x0
|
|
0x00b4 0x14 0x0
|
|
0x0158 0x01 0x0
|
|
0x0074 0x06 0x0
|
|
0x007c 0x16 0x0
|
|
0x0084 0x36 0x0
|
|
0x0078 0x06 0x0
|
|
0x0080 0x16 0x0
|
|
0x0088 0x36 0x0
|
|
0x01b0 0x1e 0x0
|
|
0x01ac 0xb9 0x0
|
|
0x01b8 0x18 0x0
|
|
0x01b4 0x94 0x0
|
|
0x0050 0x07 0x0
|
|
0x0010 0x00 0x0
|
|
0x001c 0x31 0x0
|
|
0x0020 0x01 0x0
|
|
0x0024 0xde 0x0
|
|
0x0028 0x07 0x0
|
|
0x0030 0x4c 0x0
|
|
0x0034 0x06 0x0
|
|
0x029c 0x12 0x0
|
|
0x0284 0x35 0x0
|
|
0x023c 0x11 0x0
|
|
0x051c 0x03 0x0
|
|
0x0518 0x1c 0x0
|
|
0x0524 0x1e 0x0
|
|
0x04e8 0x00 0x0
|
|
0x04ec 0x0e 0x0
|
|
0x04f0 0x4a 0x0
|
|
0x04f4 0x0f 0x0
|
|
0x05b4 0x04 0x0
|
|
0x0434 0x7f 0x0
|
|
0x0444 0x70 0x0
|
|
0x0510 0x17 0x0
|
|
0x04d4 0x54 0x0
|
|
0x04d8 0x07 0x0
|
|
0x0598 0xd4 0x0
|
|
0x059c 0x54 0x0
|
|
0x05a0 0xdb 0x0
|
|
0x05a4 0x3b 0x0
|
|
0x05a8 0x31 0x0
|
|
0x0584 0x24 0x0
|
|
0x0588 0xe4 0x0
|
|
0x058c 0xec 0x0
|
|
0x0590 0x3b 0x0
|
|
0x0594 0x36 0x0
|
|
0x0570 0xff 0x0
|
|
0x0574 0xff 0x0
|
|
0x0578 0xff 0x0
|
|
0x057c 0x7f 0x0
|
|
0x0580 0x66 0x0
|
|
0x04fc 0x00 0x0
|
|
0x04f8 0xc0 0x0
|
|
0x0460 0x30 0x0
|
|
0x0464 0xc0 0x0
|
|
0x05bc 0x0c 0x0
|
|
0x04dc 0x0d 0x0
|
|
0x0408 0x0c 0x0
|
|
0x0414 0x03 0x0
|
|
0x09a4 0x01 0x0
|
|
0x0c90 0x00 0x0
|
|
0x0c40 0x01 0x0
|
|
0x0c48 0x01 0x0
|
|
0x0c50 0x00 0x0
|
|
0x0cbc 0x00 0x0
|
|
0x0ce0 0x58 0x0
|
|
0x0048 0x90 0x0
|
|
0x0c1c 0xc1 0x0
|
|
0x0988 0x88 0x0
|
|
0x0998 0x0b 0x0
|
|
0x08dc 0x0d 0x0
|
|
0x09ec 0x01 0x0
|
|
0x0800 0x00 0x0
|
|
0x0844 0x03 0x0>;
|
|
};
|
|
|
|
&pcie1 {
|
|
reg = <0x1c08000 0x4000>,
|
|
<0x1c0e000 0x2000>,
|
|
<0x40000000 0xf1d>,
|
|
<0x40000f20 0xa8>,
|
|
<0x40001000 0x1000>,
|
|
<0x40100000 0x100000>,
|
|
<0x40200000 0x100000>,
|
|
<0x40300000 0x1fd00000>,
|
|
<0x01c0b000 0x1000>;
|
|
|
|
qcom,pcie-phy-ver = <2109>;
|
|
|
|
qcom,phy-sequence = <0x0a40 0x03 0x0
|
|
0x0010 0x00 0x0
|
|
0x001c 0x31 0x0
|
|
0x0020 0x01 0x0
|
|
0x0024 0xde 0x0
|
|
0x0028 0x07 0x0
|
|
0x0030 0x4c 0x0
|
|
0x0034 0x06 0x0
|
|
0x0048 0x90 0x0
|
|
0x0058 0x0f 0x0
|
|
0x0074 0x06 0x0
|
|
0x0078 0x06 0x0
|
|
0x007c 0x16 0x0
|
|
0x0080 0x16 0x0
|
|
0x0084 0x36 0x0
|
|
0x0088 0x36 0x0
|
|
0x0094 0x08 0x0
|
|
0x00a4 0x42 0x0
|
|
0x00ac 0x0a 0x0
|
|
0x00b0 0x1a 0x0
|
|
0x00b4 0x14 0x0
|
|
0x00b8 0x34 0x0
|
|
0x00bc 0x82 0x0
|
|
0x00c4 0x68 0x0
|
|
0x00cc 0x55 0x0
|
|
0x00d0 0x55 0x0
|
|
0x00d4 0x03 0x0
|
|
0x00d8 0xab 0x0
|
|
0x00dc 0xaa 0x0
|
|
0x00e0 0x02 0x0
|
|
0x010c 0x02 0x0
|
|
0x0110 0x24 0x0
|
|
0x0118 0xb4 0x0
|
|
0x011c 0x03 0x0
|
|
0x0154 0x34 0x0
|
|
0x0158 0x01 0x0
|
|
0x016c 0x08 0x0
|
|
0x01ac 0xb9 0x0
|
|
0x01b0 0x1e 0x0
|
|
0x01b4 0x94 0x0
|
|
0x01b8 0x18 0x0
|
|
0x01bc 0x11 0x0
|
|
0x023c 0x11 0x0
|
|
0x0284 0x35 0x0
|
|
0x029c 0x12 0x0
|
|
0x0304 0x02 0x0
|
|
0x0408 0x0c 0x0
|
|
0x0414 0x03 0x0
|
|
0x0434 0x7f 0x0
|
|
0x0444 0x70 0x0
|
|
0x0460 0x30 0x0
|
|
0x0464 0x00 0x0
|
|
0x04d4 0x04 0x0
|
|
0x04d8 0x07 0x0
|
|
0x04dc 0x0d 0x0
|
|
0x04e8 0x00 0x0
|
|
0x04ec 0x0e 0x0
|
|
0x04f0 0x4a 0x0
|
|
0x04f4 0x0f 0x0
|
|
0x04f8 0xc0 0x0
|
|
0x04fc 0x00 0x0
|
|
0x0510 0x17 0x0
|
|
0x0518 0x1c 0x0
|
|
0x051c 0x03 0x0
|
|
0x0524 0x1e 0x0
|
|
0x0570 0xff 0x0
|
|
0x0574 0xff 0x0
|
|
0x0578 0xff 0x0
|
|
0x057c 0x7f 0x0
|
|
0x0580 0x66 0x0
|
|
0x0584 0x24 0x0
|
|
0x0588 0xe4 0x0
|
|
0x058c 0xec 0x0
|
|
0x0590 0x3b 0x0
|
|
0x0594 0x36 0x0
|
|
0x0598 0xd4 0x0
|
|
0x059c 0x54 0x0
|
|
0x05a0 0xdb 0x0
|
|
0x05a4 0x3b 0x0
|
|
0x05a8 0x31 0x0
|
|
0x05bc 0x0c 0x0
|
|
0x063c 0x11 0x0
|
|
0x0684 0x35 0x0
|
|
0x069c 0x12 0x0
|
|
0x0704 0x20 0x0
|
|
0x0808 0x0c 0x0
|
|
0x0814 0x03 0x0
|
|
0x0834 0x7f 0x0
|
|
0x0844 0x70 0x0
|
|
0x0860 0x30 0x0
|
|
0x0864 0x00 0x0
|
|
0x08d4 0x04 0x0
|
|
0x08d8 0x07 0x0
|
|
0x08dc 0x0d 0x0
|
|
0x08e8 0x00 0x0
|
|
0x08ec 0x0e 0x0
|
|
0x08f0 0x4a 0x0
|
|
0x08f4 0x0f 0x0
|
|
0x08f8 0xc0 0x0
|
|
0x08fc 0x00 0x0
|
|
0x0910 0x17 0x0
|
|
0x0918 0x1c 0x0
|
|
0x091c 0x03 0x0
|
|
0x0924 0x1e 0x0
|
|
0x0970 0xff 0x0
|
|
0x0974 0xff 0x0
|
|
0x0978 0xff 0x0
|
|
0x097c 0x7f 0x0
|
|
0x0980 0x66 0x0
|
|
0x0984 0x24 0x0
|
|
0x0988 0xe4 0x0
|
|
0x098c 0xec 0x0
|
|
0x0990 0x3b 0x0
|
|
0x0994 0x36 0x0
|
|
0x0998 0xd4 0x0
|
|
0x099c 0x54 0x0
|
|
0x09a0 0xdb 0x0
|
|
0x09a4 0x3b 0x0
|
|
0x09a8 0x31 0x0
|
|
0x09bc 0x0c 0x0
|
|
0x0adc 0x05 0x0
|
|
0x0b88 0x88 0x0
|
|
0x0b98 0x0b 0x0
|
|
0x0ba4 0x01 0x0
|
|
0x0bec 0x12 0x0
|
|
0x0e0c 0x0d 0x0
|
|
0x0e14 0x07 0x0
|
|
0x0e1c 0xc1 0x0
|
|
0x0e40 0x01 0x0
|
|
0x0e48 0x01 0x0
|
|
0x0e90 0x00 0x0
|
|
0x0eb4 0x33 0x0
|
|
0x0ebc 0x00 0x0
|
|
0x0ee0 0x58 0x0
|
|
0x0ea4 0x0f 0x0
|
|
0x0a00 0x00 0x0
|
|
0x0a44 0x03 0x0>;
|
|
};
|
|
|
|
&msm_fastrpc {
|
|
qcom,msm_fastrpc_compute_cb1 {
|
|
iommus = <&apps_smmu 0x1001 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb2 {
|
|
iommus = <&apps_smmu 0x1002 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb3 {
|
|
iommus = <&apps_smmu 0x1003 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb4 {
|
|
iommus = <&apps_smmu 0x1004 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb5 {
|
|
iommus = <&apps_smmu 0x1005 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb6 {
|
|
iommus = <&apps_smmu 0x1006 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb7 {
|
|
iommus = <&apps_smmu 0x1007 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb8 {
|
|
iommus = <&apps_smmu 0x1008 0x0460>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb9 {
|
|
iommus = <&apps_smmu 0x1009 0x0460>;
|
|
};
|
|
};
|
|
|
|
/* GPU overrides */
|
|
&msm_gpu {
|
|
/* Updated chip ID */
|
|
qcom,chipid = <0x06040001>;
|
|
|
|
/* Power level to start throttling */
|
|
qcom,throttle-pwrlevel = <0>;
|
|
|
|
qcom,bus-table-ddr =
|
|
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
|
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
|
<MHZ_TO_KBPS(300, 4)>, /* index=2 */
|
|
<MHZ_TO_KBPS(451, 4)>, /* index=3 */
|
|
<MHZ_TO_KBPS(547, 4)>, /* index=4 */
|
|
<MHZ_TO_KBPS(681, 4)>, /* index=5 */
|
|
<MHZ_TO_KBPS(768, 4)>, /* index=6 */
|
|
<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
|
|
<MHZ_TO_KBPS(1353, 4)>, /* index=8 */
|
|
<MHZ_TO_KBPS(1555, 4)>, /* index=9 */
|
|
<MHZ_TO_KBPS(1804, 4)>, /* index=10 */
|
|
<MHZ_TO_KBPS(2092, 4)>; /* index=11 */
|
|
|
|
qcom,bus-table-cnoc =
|
|
<0>, /* Off */
|
|
<100>; /* On */
|
|
|
|
qcom,gpu-speed-bin = <0x4130 0xe0000000 29>;
|
|
|
|
/delete-property/qcom,initial-pwrlevel;
|
|
/delete-node/qcom,gpu-pwrlevels;
|
|
qcom,gpu-pwrlevel-bins {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compatible="qcom,gpu-pwrlevel-bins";
|
|
qcom,gpu-pwrlevels-0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <0>;
|
|
qcom,initial-pwrlevel = <4>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <585000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
qcom,bus-freq = <11>;
|
|
qcom,bus-min = <11>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <499200000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <8>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <427000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
qcom,bus-freq = <6>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <345000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <257000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <2>;
|
|
qcom,bus-max = <4>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <5>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
|
|
|
|
qcom,gpu-pwrlevels-1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <1>;
|
|
qcom,initial-pwrlevel = <5>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <675000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
qcom,bus-freq = <11>;
|
|
qcom,bus-min = <11>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <585000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
qcom,bus-freq = <10>;
|
|
qcom,bus-min = <9>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <499200000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <8>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <427000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
qcom,bus-freq = <6>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <345000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
qcom,bus-freq = <4>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <5>;
|
|
qcom,gpu-freq = <257000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <2>;
|
|
qcom,bus-max = <4>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <6>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,l3-pwrlevels {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
compatible = "qcom,l3-pwrlevels";
|
|
|
|
qcom,l3-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,l3-freq = <0>;
|
|
};
|
|
|
|
qcom,l3-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,l3-freq = <1344000000>;
|
|
};
|
|
|
|
qcom,l3-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,l3-freq = <1612800000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gmu {
|
|
reg = <0x2c6a000 0x30000>,
|
|
<0xb290000 0x10000>,
|
|
<0xb490000 0x10000>;
|
|
reg-names = "kgsl_gmu_reg",
|
|
"kgsl_gmu_pdc_cfg",
|
|
"kgsl_gmu_pdc_seq";
|
|
};
|
|
|
|
&msm_vidc {
|
|
qcom,allowed-clock-rates = <240000000 338000000
|
|
365000000 444000000 533000000>;
|
|
|
|
non_secure_cb {
|
|
iommus = <&apps_smmu 0x2300 0x60>;
|
|
};
|
|
secure_bitstream_cb {
|
|
iommus = <&apps_smmu 0x2301 0x4>;
|
|
};
|
|
secure_pixel_cb {
|
|
iommus = <&apps_smmu 0x2303 0x20>;
|
|
};
|
|
secure_non_pixel_cb {
|
|
iommus = <&apps_smmu 0x2304 0x60>;
|
|
};
|
|
};
|
|
|
|
/* NPU overrides */
|
|
&msm_npu {
|
|
iommus = <&apps_smmu 0x1081 0x400>;
|
|
qcom,npu-pwrlevels {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "qcom,npu-pwrlevels";
|
|
initial-pwrlevel = <5>;
|
|
qcom,npu-pwrlevel@0 {
|
|
reg = <0>;
|
|
vreg = <1>;
|
|
clk-freq = <0
|
|
0
|
|
0
|
|
100000000
|
|
300000000
|
|
300000000
|
|
19200000
|
|
150000000
|
|
100000000
|
|
37500000
|
|
19200000
|
|
60000000
|
|
100000000
|
|
19200000
|
|
19200000
|
|
0
|
|
19200000
|
|
300000000
|
|
19200000
|
|
19200000>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@1 {
|
|
reg = <1>;
|
|
vreg = <2>;
|
|
clk-freq = <0
|
|
0
|
|
0
|
|
150000000
|
|
400000000
|
|
400000000
|
|
37500000
|
|
200000000
|
|
150000000
|
|
75000000
|
|
19200000
|
|
120000000
|
|
150000000
|
|
19200000
|
|
19200000
|
|
0
|
|
19200000
|
|
400000000
|
|
19200000
|
|
19200000>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@2 {
|
|
reg = <2>;
|
|
vreg = <3>;
|
|
clk-freq = <0
|
|
0
|
|
0
|
|
200000000
|
|
487000000
|
|
487000000
|
|
37500000
|
|
300000000
|
|
200000000
|
|
150000000
|
|
19200000
|
|
240000000
|
|
200000000
|
|
19200000
|
|
19200000
|
|
0
|
|
19200000
|
|
487000000
|
|
19200000
|
|
19200000>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@3 {
|
|
reg = <3>;
|
|
vreg = <4>;
|
|
clk-freq = <0
|
|
0
|
|
0
|
|
300000000
|
|
652000000
|
|
652000000
|
|
75000000
|
|
403000000
|
|
300000000
|
|
150000000
|
|
19200000
|
|
240000000
|
|
300000000
|
|
19200000
|
|
19200000
|
|
0
|
|
19200000
|
|
652000000
|
|
19200000
|
|
19200000>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@4 {
|
|
reg = <4>;
|
|
vreg = <6>;
|
|
clk-freq = <0
|
|
0
|
|
0
|
|
400000000
|
|
811000000
|
|
811000000
|
|
75000000
|
|
533000000
|
|
400000000
|
|
150000000
|
|
19200000
|
|
300000000
|
|
400000000
|
|
19200000
|
|
19200000
|
|
0
|
|
19200000
|
|
811000000
|
|
19200000
|
|
19200000>;
|
|
};
|
|
|
|
qcom,npu-pwrlevel@5 {
|
|
reg = <5>;
|
|
vreg = <7>;
|
|
clk-freq = <0
|
|
0
|
|
0
|
|
400000000
|
|
908000000
|
|
908000000
|
|
75000000
|
|
533000000
|
|
400000000
|
|
150000000
|
|
19200000
|
|
300000000
|
|
400000000
|
|
19200000
|
|
19200000
|
|
0
|
|
19200000
|
|
908000000
|
|
19200000
|
|
19200000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "camera/sm8150-v2-camera.dtsi"
|