No description
  • C 98.2%
  • Assembly 1%
  • Makefile 0.3%
  • Shell 0.2%
  • Python 0.1%
Find a file
Repository files (latest commit first)
Filename Latest commit message Latest commit date
Yashwanth fc9b0e31fb disp: msm: sde: add cached lut flag in sde plane
Below is the sequence during which issue is observed
while using stale lut values:

1) Scaler block is enabled in the VIG pipe along with the
valid lut configuration.

2) Idle work gets scheduled and GDSC is turned off erasing
the saved lut values.

3) At the same time, userspace sends a commit assuming lut
values are still valid resulting in artifacts on the
screen.

In the plane state scaler config, only lut flag will be
reset for subsequent commits and remaining properties such
as filter cfgs, lut_idx etc. remains same. This change
caches the lut flag in sde plane whenever the lut is being
set and reuses this flag to handle above issue.

Change-Id: Ice22f811ecc8094834f66e2020d33b01bb951bb0
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-03-10 15:51:28 +05:30
config disp: msm: make msm_drm as module for normal builds 2021-02-17 13:24:13 -08:00
hdcp
include disp: msm: parse SPMI registers and append to IO lend list 2020-08-17 09:47:28 -07:00
msm disp: msm: sde: add cached lut flag in sde plane 2021-03-10 15:51:28 +05:30
rotator Merge "disp: msm: register rotator platform driver after genpd init" 2020-09-28 04:39:41 -07:00
Android.bp techpack: Install headers for display techpack 2020-12-17 13:50:14 -08:00
display_kernel_headers.py display: Use sh to execute install script 2021-02-08 15:50:05 -05:00
Makefile Merge "Revert "disp: fix compilation issue with trusted VM config"" 2020-07-21 13:18:32 -07:00
NOTICE