mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
13cddf25e6
Add the following clocks to the list of clocks to vote for in order to access the KGSL SMMU register space: - GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK - GPU_CC_CX_GMU_CLK - GPU_CC_HUB_CX_INT_CLK - GPU_CC_HUB_AON_CLK. Change-Id: I3b41afc2e01470318ebf21edc2bb78b0421c76db
373 lines
11 KiB
Devicetree
373 lines
11 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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kgsl_smmu: kgsl-smmu@3da0000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x3DA0000 0x20000>,
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<0x3DC2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,split-tables;
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#global-interrupts = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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dma-coherent;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cc_cx_gdsc>;
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clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>,
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<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&clock_gpucc GPU_CC_CX_GMU_CLK>,
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<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&clock_gpucc GPU_CC_HUB_AON_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb",
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"gpu_cc_hlos1_vote_gpu_smmu_clk",
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"gpu_cc_cx_gmu_clk",
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"gpu_cc_hub_cx_int_clk",
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"gpu_cc_hub_aon_clk";
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interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;
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qcom,actlr =
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/* All CBs of GFX: +15 deep PF */
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<0x0 0x400 0x32B>,
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<0x1 0x400 0x32B>,
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<0x2 0x400 0x32B>,
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<0x4 0x400 0x32B>,
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<0x5 0x400 0x32B>,
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<0x7 0x400 0x32B>;
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interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
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gfx_0_tbu: gfx_0_tbu@3dc5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x3DC5000 0x1000>,
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<0x3DC2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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};
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gfx_1_tbu: gfx_1_tbu@3dc9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x3DC9000 0x1000>,
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<0x3DC2208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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};
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};
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apps_smmu: apps-smmu@15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x100000>,
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<0x15182000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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#global-interrupts = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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dma-coherent;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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qcom,actlr =
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/* For HF-0 TBU +3 deep PF */
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<0x800 0x3FF 0x103>,
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/* For HF-1 TBU +3 deep PF */
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<0xC00 0x3FF 0x103>,
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/* For Compute-1 TBU +15 deep PF */
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<0x1000 0x3FF 0x303>,
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/* For Compute-0 TBU +15 deep PF */
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<0x1400 0x3FF 0x303>,
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/* For SF-[0/1] TBU Compute clients +15 deep PF */
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<0x126 0x34C0 0x303>,
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<0x12D 0x24C0 0x303>,
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<0x144 0x2420 0x303>,
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<0x148 0x3420 0x303>,
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<0x149 0x34A0 0x303>,
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<0x14C 0x34A0 0x303>,
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<0x16F 0x3480 0x303>,
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<0x2142 0x4A0 0x303>,
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<0x2143 0x14A0 0x303>,
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<0x2147 0x420 0x303>,
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<0x2161 0x400 0x303>,
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<0x2165 0x480 0x303>,
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<0x216B 0x1400 0x303>,
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<0x216E 0x400 0x303>,
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/* For SF-[0/1] TBU Camera clients +3 deep PF */
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<0x2000 0x4FF 0x103>,
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/* For SF-[0/1] TBU Video clients +3 deep PF */
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<0x2100 0x403 0x103>,
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<0x2104 0x400 0x103>,
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/* For SF-[0/1] TBU CVP clients +3 deep PF */
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<0x2120 0x403 0x103>,
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<0x2124 0x400 0x103>,
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/* For SF-[0/1] TBU Display clients +3 deep PF */
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<0x215C 0x401 0x103>;
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anoc_1_tbu: anoc_1_tbu@15185000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15185000 0x1000>,
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<0x15182200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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};
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anoc_2_tbu: anoc_2_tbu@15189000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15189000 0x1000>,
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<0x15182208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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};
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mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x1518D000 0x1000>,
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<0x15182210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
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interconnects = <&mmss_noc MASTER_MDP0
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15191000 0x1000>,
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<0x15182218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
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interconnects = <&mmss_noc MASTER_MDP0
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15195000 0x1000>,
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<0x15182220 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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interconnects = <&nsp_noc MASTER_CDSP_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x15199000 0x1000>,
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<0x15182228 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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interconnects = <&nsp_noc MASTER_CDSP_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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adsp_tbu: adsp_tbu@1519d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x1519D000 0x1000>,
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<0x15182230 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1800 0x400>;
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};
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anoc_1_pcie_tbu: anoc_1_pcie_tbu@151a1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151A1000 0x1000>,
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<0x15182238 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1c00 0x400>;
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clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
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clock-names = "gcc_aggre_noc_pcie_tbu_clk";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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};
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mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151A5000 0x1000>,
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<0x15182240 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2000 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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mnoc_sf_1_tbu: mnoc_sf_1_tbu@151a9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151A9000 0x1000>,
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<0x15182248 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2400 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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};
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kgsl_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x7 0>;
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qcom,iommu-dma = "disabled";
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};
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kgsl_iommu_coherent_test_device {
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status = "disabled";
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x9 0>;
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qcom,iommu-dma = "disabled";
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dma-coherent;
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};
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apps_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x7E0 0>;
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qcom,iommu-dma = "disabled";
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};
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apps_iommu_coherent_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x7E1 0>;
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qcom,iommu-dma = "disabled";
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dma-coherent;
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};
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};
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