Repository files (latest commit first)

Filename	Latest commit message	Latest commit date
Govind Singh bc679dc919 qcacmn: Do not allow CE register access when recovery is in progress ... Currently, Shadow registers is not implemented for all registers. This can lead to unclocked access and followed by NOC errors. In Rx path Interrupt Status and src/dst read index are directly accessed without shadow block. Target may execute reset sequence due to PDR/SSR while rx path is active. Avoid direct access to below registers if target is crashed due to PDR/SSR. HOST_IE_ADDRESS HOST_IS_ADDRESS CURRENT_DRRI_ADDRESS CURRENT_SRRI_ADDRESS Return from ISR without scheduling the bottom half if target is crashed due to PDR/SSR. Change-Id: Ifa993e978579b4d061d21281338494292e19700a CRs-Fixed: 2123967		2017-10-12 14:22:34 -07:00
..
hif.h	qcacmn: Do not allow CE register access when recovery is in progress	2017-10-12 14:22:34 -07:00
hif_unit_test_suspend.h	qcacmn: Refactor Unit-Test Suspend	2017-06-16 09:49:14 -07:00
host_reg_init.h	qcacmn: Add support for Regtable convergence	2016-05-19 17:59:43 -07:00
hostdef.h	qcacmn: Support QCA6290 target type	2016-11-19 06:47:36 -08:00
reg_struct.h	qcacmn: WAR for CE status ring timer intr issue	2017-06-12 17:19:24 -07:00
regtable.h	qcacmn: Add USB bus support (HIF Common)	2016-08-17 12:05:38 -07:00
regtable_pcie.h	qcacmn: add 'const' for 'section' in struct TGT_REG_TABLE	2017-06-09 17:23:40 -07:00
target_reg_init.h	qcacmn: WAR for CE status ring timer intr issue	2017-06-12 17:19:24 -07:00
targetdef.h	qcacmn: Support QCA6290 target type	2016-11-19 06:47:36 -08:00