mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
573cab957b
The IOMMU page table management code is not optimal from a performance perspective in the GKI configuration, relative to the downstream implementation. When the GPU enters slumber, and requests the SMMU driver to unmap memory from the stage 1 page tables of the GPU. When unmapping memory, the SMMU driver must access the GPU SMMU's register space, so it must vote for power resources to access the TLB invalidation registers. When the GPU is in slumber, there aren't votes for the GPU SMMU's power resources, so the SMMU driver constantly ends up enabling/disabling the power resources, which takes a considerable amount of time. When paired with the suboptimal IOMMU page table management code, this leads to performance issues where the time taken to unmap memory is large. Thus, for all targets that support GKI, add the qcom,power-always-on property for the GPU SMMUs of these targets, to remove the latency incurred by having to enable/disable power resources in the GKI configuration. Change-Id: Id3237214e44c008871d01ec6652b08c4fb24e41c
214 lines
6.4 KiB
Devicetree
214 lines
6.4 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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kgsl_smmu: arm,smmu-kgsl@5940000 {
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compatible = "qcom,smmu-v2";
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reg = <0x5940000 0x10000>;
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#iommu-cells = <1>;
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qcom,use-3-lvl-tables;
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#global-interrupts = <2>;
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qcom,power-always-on;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cx_gdsc>;
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clock-names = "gcc_gpu_memnoc_gfx_clk";
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
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attach-impl-defs =
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<0x6000 0x2378>,
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<0x6060 0x1055>,
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<0x678c 0x8>,
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<0x6794 0x28>,
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<0x6800 0x6>,
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<0x6900 0x3ff>,
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<0x6924 0x204>,
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<0x6928 0x11000>,
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<0x6930 0x800>,
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<0x6960 0xffffffff>,
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<0x6b64 0x1a5551>,
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<0x6b68 0x9a82a382>;
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};
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apps_smmu: apps-smmu@0c600000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x0c600000 0x100000>,
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<0x0c702000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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#global-interrupts = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,actlr =
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/* For rt TBU camera +3 deep PF */
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<0x800 0x3ff 0x103>,
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/* For nrt TBU +3 deep PF */
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<0xc00 0x3ff 0x103>,
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/* For anoc_1 TBU disable PF */
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<0x0 0x3ff 0x001>;
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anoc_1_tbu: anoc_1_tbu@0c705000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x0c705000 0x1000>,
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<0x0c702200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&config_noc SLAVE_IMEM_CFG>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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};
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anoc_2_tbu: anoc_2_tbu@0c709000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x0c709000 0x1000>,
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<0x0c702208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&config_noc SLAVE_IMEM_CFG>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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};
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mm_rt_tbu: mm_rt_tbu@0c70d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x0c70d000 0x1000>,
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<0x0c702210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>;
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interconnects = <&mmrt_virt MASTER_MDP_PORT0
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&bimc SLAVE_EBI>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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};
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mm_nrt_tbu: mm_nrt_tbu@0c711000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x0c711000 0x1000>,
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<0x0c702218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>;
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interconnects = <&mmnrt_virt MASTER_CAMNOC_SF
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&bimc SLAVE_EBI>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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};
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compute_dsp_tbu: compute_dsp_0_tbu@0c715000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x0c715000 0x1000>,
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<0x0c702220 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>;
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interconnects = <&bimc MASTER_CDSP_PROC
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&bimc SLAVE_EBI>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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};
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};
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kgsl_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x7>;
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qcom,iommu-dma = "disabled";
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};
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apps_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x100 0>;
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qcom,iommu-dma = "disabled";
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};
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};
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