mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
84a95d00e0
Fix compilation warnings for sa8155, sa8195 and sa6155. Change-Id: I6463b9106e2c40104720052b073455164e641df1
208 lines
4.4 KiB
Devicetree
208 lines
4.4 KiB
Devicetree
#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-scshrike.h>
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#include "sa8195p-cnss.dtsi"
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&qupv3_3 {
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status = "ok"
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};
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&qupv3_se0_spi {
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status = "ok"
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#address-cells = <1>;
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#size-cells = <0>;
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can-controller@0 {
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compatible = "qcom,nxp,mpc5746c";
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reg = <0>;
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interrupt-parent = <&tlmm>;
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interrupts = <38 0>;
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spi-max-frequency = <5000000>;
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qcom,clk-freq-mhz = <40000000>;
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qcom,max-can-channels = <1>;
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qcom,bits-per-word = <8>;
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qcom,support-can-fd;
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};
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};
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&qupv3_se12_2uart {
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status = "ok"
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};
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&sdhc_2 {
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vdd-supply = <&pm8195_1_l10>;
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qcom,vdd-voltage-level = <2950000 2960000>;
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qcom,vdd-current-level = <200 800000>;
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vdd-io-supply = <&pm8195_1_l2>;
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qcom,vdd-io-voltage-level = <1808000 2960000>;
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qcom,vdd-io-current-level = <200 22000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;
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status = "ok"
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};
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&soc {
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qcom,lpass@17300000 {
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status = "ok"
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qcom,pil-force-shutdown;
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};
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qcom,turing@8300000 {
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status = "ok"
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};
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qcom,venus@aae0000 {
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status = "ok"
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};
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qcom,spss@188101c {
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status = "ok"
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};
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qcom,npu@9800000 {
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status = "ok"
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <4>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x0>;
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snps,route-up;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,map-to-dma-channel = <0x1>;
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snps,route-ptp;
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};
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queue2 {
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snps,avb-algorithm;
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snps,map-to-dma-channel = <0x2>;
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snps,route-avcp;
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};
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queue3 {
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snps,avb-algorithm;
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snps,map-to-dma-channel = <0x3>;
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snps,priority = <0xC>;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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snps,tx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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};
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queue1 {
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snps,dcb-algorithm;
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};
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queue2 {
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snps,avb-algorithm;
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snps,send_slope = <0x1000>;
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snps,idle_slope = <0x1000>;
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snps,high_credit = <0x3E800>;
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snps,low_credit = <0xFFC18000>;
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};
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queue3 {
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snps,avb-algorithm;
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snps,send_slope = <0x1000>;
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snps,idle_slope = <0x1000>;
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snps,high_credit = <0x3E800>;
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snps,low_credit = <0xFFC18000>;
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};
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};
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ethqos_hw: qcom,ethernet@20000 {
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compatible = "qcom,stmmac-ethqos";
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qcom,arm-smmu;
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emac-core-version = <0x20010001>;
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reg = <0x20000 0x10000>,
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<0x36000 0x100>,
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<0x3D00000 0x300000>;
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reg-names = "stmmaceth", "rgmii","tlmm-central-base";
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clocks = <&gcc GCC_EMAC_AXI_CLK>,
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<&gcc GCC_EMAC_SLV_AHB_CLK>,
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<&gcc GCC_EMAC_PTP_CLK>,
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<&gcc GCC_EMAC_RGMII_CLK>;
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clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
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snps,ptp-ref-clk-rate = <250000000>;
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snps,ptp-req-clk-rate = <96000000>;
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interrupts-extended = <&intc 0 689 4>, <&intc 0 700 4>,
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<&tlmm 124 2>;
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interrupt-names = "macirq", "eth_lpi",
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"phy-intr";
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snps,tso;
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rx-fifo-depth = <16384>;
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tx-fifo-depth = <32768>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>;
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qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>;
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gdsc_emac-supply = <&emac_gdsc>;
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pinctrl-names = "dev-emac-mdc",
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"dev-emac-mdio",
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"dev-emac-rgmii_txd0_state",
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"dev-emac-rgmii_txd1_state",
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"dev-emac-rgmii_txd2_state",
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"dev-emac-rgmii_txd3_state",
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"dev-emac-rgmii_txc_state",
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"dev-emac-rgmii_tx_ctl_state",
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"dev-emac-rgmii_rxd0_state",
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"dev-emac-rgmii_rxd1_state",
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"dev-emac-rgmii_rxd2_state",
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"dev-emac-rgmii_rxd3_state",
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"dev-emac-rgmii_rxc_state",
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"dev-emac-rgmii_rx_ctl_state",
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"dev-emac-phy_intr",
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"dev-emac-phy_reset_state",
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"dev-emac_pin_pps_0";
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pinctrl-0 = <&emac_mdc>;
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pinctrl-1 = <&emac_mdio>;
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pinctrl-2 = <&emac_rgmii_txd0>;
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pinctrl-3 = <&emac_rgmii_txd1>;
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pinctrl-4 = <&emac_rgmii_txd2>;
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pinctrl-5 = <&emac_rgmii_txd3>;
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pinctrl-6 = <&emac_rgmii_txc>;
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pinctrl-7 = <&emac_rgmii_tx_ctl>;
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pinctrl-8 = <&emac_rgmii_rxd0>;
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pinctrl-9 = <&emac_rgmii_rxd1>;
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pinctrl-10 = <&emac_rgmii_rxd2>;
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pinctrl-11 = <&emac_rgmii_rxd3>;
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pinctrl-12 = <&emac_rgmii_rxc>;
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pinctrl-13 = <&emac_rgmii_rx_ctl>;
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pinctrl-14 = <&emac_phy_intr>;
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pinctrl-15 = <&emac_phy_reset_state>;
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pinctrl-16 = <&emac_pin_pps_0>;
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snps,reset-delays-us = <0 11000 70000>;
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phy-mode = "rgmii";
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ethqos_emb_smmu: ethqos_emb_smmu {
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compatible = "qcom,emac-smmu-embedded";
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iommus = <&apps_smmu 0x7C0 0x0>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>;
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};
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};
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};
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