436 lines
16 KiB
Text
436 lines
16 KiB
Text
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* ARM System MMU Architecture Implementation
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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** System MMU required properties:
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- compatible : Should be one of:
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"arm,smmu-v1"
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"arm,smmu-v2"
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"arm,mmu-400"
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"arm,mmu-401"
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"arm,mmu-500"
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"cavium,smmu-v2"
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"qcom,qsmmu-v500"
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"qcom,adreno-smmu"
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"qcom,smmu-v2"
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"qcom,virt-smmu"
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depending on the particular implementation and/or the
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version of the architecture implemented.
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Qcom SoCs must contain, as below, SoC-specific compatibles
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along with "qcom,smmu-v2":
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"qcom,msm8996-smmu-v2", "qcom,smmu-v2",
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"qcom,sdm845-smmu-v2", "qcom,smmu-v2".
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Qcom SoCs implementing "arm,mmu-500" must also include,
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as below, SoC-specific compatibles:
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"qcom,sdm845-smmu-500", "arm,mmu-500"
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"qcom,virt-smmu" is a subtype of "qcom,qsmmu-v500" which
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only supports access to the set of registers required by
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the arm specificiation. None of the additional registers
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normally present in qcom,qsmmu-v500 are supported
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currently.
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- reg : Base address and size of the SMMU.
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- reg-names : For the "qcom,qsmmu-v500" device "tcu-base" is expected.
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- #global-interrupts : The number of global interrupts exposed by the
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device.
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- interrupts : Interrupt list, with the first #global-irqs entries
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corresponding to the global interrupts and any
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following entries corresponding to context interrupts,
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specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one
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interrupt per context bank. In the case of a single,
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combined interrupt, it must be listed multiple times.
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- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
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for details. With a value of 1, each IOMMU specifier
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represents a distinct stream ID emitted by that device
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into the relevant SMMU.
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SMMUs with stream matching support and complex masters
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may use a value of 2, where the second cell of the
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IOMMU specifier represents an SMR mask to combine with
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the ID in the first cell. Care must be taken to ensure
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the set of matched IDs does not result in conflicts.
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** System MMU optional properties:
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- dma-coherent : Present if page table walks made by the SMMU are
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cache coherent with the CPU.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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- calxeda,smmu-secure-config-access : Enable proper handling of buggy
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implementations that always use secure access to
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SMMU configuration registers. In this case non-secure
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aliases of secure registers have to be used during
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SMMU configuration.
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- stream-match-mask : For SMMUs supporting stream matching and using
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#iommu-cells = <1>, specifies a mask of bits to ignore
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when matching stream IDs (e.g. this may be programmed
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into the SMRn.MASK field of every stream match register
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used). For cases where it is desirable to ignore some
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portion of every Stream ID (e.g. for certain MMU-500
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configurations given globally unique input IDs). This
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property is not valid for SMMUs using stream indexing,
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or using stream matching with #iommu-cells = <2>, and
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may be ignored if present in such cases.
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- clock-names: List of the names of clocks input to the device. The
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required list depends on particular implementation and
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is as follows:
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- for "qcom,smmu-v2":
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- "bus": clock required for downstream bus access and
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for the smmu ptw,
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- "iface": clock required to access smmu's registers
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through the TCU's programming interface.
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- unspecified for other implementations.
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- clocks: Specifiers for all clocks listed in the clock-names property,
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as per generic clock bindings.
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- power-domains: Specifiers for power domains required to be powered on for
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the SMMU to operate, as per generic power domain bindings.
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- attach-impl-defs : global registers to program at device attach
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time. This should be a list of 2-tuples of the format:
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<offset reg_value>.
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- qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware
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requires special fixups to recover from address size
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faults. Rather than applying the fixups just BUG since
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address size faults are due to a fundamental programming
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error from which we don't care about recovering anyways.
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- qcom,skip-init : Disable resetting configuration for all context banks
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during device reset. This is useful for targets where
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some context banks are dedicated to other execution
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environments outside of Linux and those other EEs are
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programming their own stream match tables, SCTLR, etc.
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Without setting this option we will trample on their
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configuration.
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- qcom,use-3-lvl-tables:
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Some hardware configurations may not be optimized for using
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a four level page table configuration. Set to use a three
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level page table instead.
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- qcom,context-fault-retry:
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Retry iommu faults after a tlb invalidate, if stall-on-fault
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is enabled.
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- qcom,no-asid-retention:
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Some hardware may lose internal state for asid after
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retention. No cache invalidation operations involving asid
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may be used.
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- qcom,split-tables:
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Some hardware configurations can easily use a model where
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the I/O virtual address space for a domain can be split into
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two symmetric portions, and clients can manage each portion.
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Set for hardware that supports this model, and requires
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this feature.
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- qcom,actlr:
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An array of <sid mask actlr-setting>.
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Any sid X for which X&~mask==sid will be programmed with the
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given actlr-setting.
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-qcom,disable-atos:
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Some hardware may not have full support for atos debugging
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in tandem with other features like power collapse.
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- (%s)-supply : Phandle of the regulator that should be powered on during
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SMMU register access. (%s) is a string from the
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qcom,regulator-names property.
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- qcom,regulator-names :
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List of strings to use with the (%s)-supply property.
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- interconnects:
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Pairs of phandles and interconnect provider specifier to
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denote the edge source and destination ports of the
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interconnect path. For more information, please see
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bindings/interconnect/interconnect.txt
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- qcom,active-only:
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Boolean property which denotes that interconnect votes
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should be maintained while the CPUSS is awake
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(active context). The absence of this property makes it so
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that interconnect votes will be maintained irrespective of
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the CPUSS' state (awake or asleep).
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- qcom,num-context-banks-override:
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Optional integer. Should be set if the hypervisor virtualization
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is disabled for debugging purposes. When this is done, some
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context banks managed by hypervisor become visible to HLOS, but should
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not be accessed.
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- qcom,num-smr-override:
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Optional integer. See qcom,num-context-banks-override.
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- qcom,multi-match-handoff-smr:
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Optional property. Should be included if one handoff SMR matches
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multiple SMRs.
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** Deprecated properties:
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- mmu-masters (deprecated in favour of the generic "iommus" binding) :
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A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding Stream IDs. Each device node
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linked from this list must have a "#stream-id-cells"
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property, indicating the number of Stream ID
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arguments associated with its phandle.
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** Additional properties for Iommu Clients:
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- qcom,iommu-dma:
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Optional, String.
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Can be one of "bypass", "fastmap", "atomic", "disabled".
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--- "default":
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Standard iommu translation behavior.
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The iommu framework will automatically create a domain for the client.
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iommu and DMA apis may not be called in atomic context.
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--- "bypass":
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DMA APIs will use 1-to-1 translation between dma_addr and phys_addr.
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Allows using iommu and DMA apis in atomic context.
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--- "fastmap":
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DMA APIs will run faster, but use several orders of magnitude more memory.
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Also allows using iommu and DMA apis in atomic context.
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--- "atomic":
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Allows using iommu and DMA apis in atomic context.
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--- "disabled":
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The iommu client is responsible for allocating an iommu domain, as
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well as calling iommu_map to create the desired mappings.
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- qcom,iommu-faults:
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Optional, List of Strings.
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The SCTLR register setting which affect iommu faults handling.
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Any combination of the below strings may be used. Mutliple
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values are accepted.
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--- "default":
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Any faults are treated as fatal errors.
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--- "no-CFRE":
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Iommu faults do not return an abort to the client hardware.
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--- "non-fatal":
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Iommu faults do not trigger a kernel panic.
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--- "stall-disable":
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Iommu faults do not stall the client while the fault
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interrupt is being handled.
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- qcom,iommu-vmid:
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Optional, Int.
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An identifier indicating the security state of the client.
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- qcom,iommu-pagetable:
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Optional, String.
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Enables coherency for the IOMMU device, but not for the Client.
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--- "default":
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Pagetable coherency defaults to the coherency setting of the
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IOMMU device.
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--- "coherent"
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Pagetables are io-coherent.
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--- "LLC"
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Pagetables may be saved in the system cache. Should not be used if
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the IOMMU device is io-coherent.
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--- "LLC_NWA"
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Pagetables may be saved in the system cache is used, and
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write-allocate hint is disabled. Should not be used if the IOMMU
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device is io-coherent.
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- qcom,iommu-earlymap:
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Optional, Bool.
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Support creating mappings in the page-table before Stage 1 translation is
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enabled.
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- qcom,iommu-dma-addr-pool:
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Optional, tuple of <address size>.
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Defaults to <0, SZ_4G> if not present.
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Indicates the range of addresses that the dma layer will use.
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- qcom,iommu-geometry:
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Optional, tuple of <address size>.
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Defaults to <0, SZ_4G> if not present.
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Indicates the available IOVA space when the qcom,iommu-dma property
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is set to "fastmap". The new space created will be a superset of
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the IOVA range which was created through the
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qcom,iommu-dma-addr-pool DT property.
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- qcom,iommu-msi-size:
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Optional, Int.
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Indicates the amount of space--in bytes--that must be reserved from
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the client's total IOVA space for mapping MSI registers when the
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qcom,iommu-dma property is set to "fastmap".
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-qcom,iommu-defer-smr-config:
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Optional, Bool.
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Indicates that the SMRs for the client should not be programmed when the
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client device is attaching to the SMMU, but when the client's device
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driver requests it at a later point in time when the client is ready for
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DMA transfers.
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** Examples:
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/* SMMU with stream matching or stream indexing */
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smmu1: iommu {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>, /* This is the first context interrupt */
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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#iommu-cells = <1>;
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};
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/* device with two stream IDs, 0 and 7 */
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master1 {
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iommus = <&smmu1 0>,
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<&smmu1 7>;
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};
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/* SMMU with stream matching */
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smmu2: iommu {
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...
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#iommu-cells = <2>;
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};
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/* device with stream IDs 0 and 7 */
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master2 {
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iommus = <&smmu2 0 0>,
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<&smmu2 7 0>;
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};
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/* device with stream IDs 1, 17, 33 and 49 */
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master3 {
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iommus = <&smmu2 1 0x30>;
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};
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/* ARM MMU-500 with 10-bit stream ID input configuration */
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smmu3: iommu {
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compatible = "arm,mmu-500", "arm,smmu-v2";
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...
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#iommu-cells = <1>;
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/* always ignore appended 5-bit TBU number */
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stream-match-mask = 0x7c00;
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};
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bus {
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/* bus whose child devices emit one unique 10-bit stream
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ID each, but may master through multiple SMMU TBUs */
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iommu-map = <0 &smmu3 0 0x400>;
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...
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};
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/* Qcom's arm,smmu-v2 implementation */
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smmu4: iommu@d00000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xd00000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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power-domains = <&mmcc MDSS_GDSC>;
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clocks = <&mmcc SMMU_MDP_AXI_CLK>,
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<&mmcc SMMU_MDP_AHB_CLK>;
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clock-names = "bus", "iface";
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};
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* Qualcomm Technologies, Inc. MMU-500 TBU Device
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The qcom,qsmmu-v500 device implements a number of register regions containing
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debug functionality. Each register region maps to a separate tbu from the
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arm mmu-500 implementation.
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||
|
|
** TBU/QTB required properties:
|
||
|
|
|
||
|
|
- compatible : Should be one of:
|
||
|
|
"qcom,qsmmuv500-tbu"
|
||
|
|
|
||
|
|
"qcom,qtb500" can be used in conjunction with
|
||
|
|
"qcom,qsmmuv500-tbu", as the QTB500 is an implementation
|
||
|
|
of a TBU with different features/enhancements than a regular
|
||
|
|
TBU.
|
||
|
|
|
||
|
|
- reg : Base address and size.
|
||
|
|
|
||
|
|
-qcom,stream-id-range:
|
||
|
|
Pair of values describing the smallest supported stream-id
|
||
|
|
and the size of the entire set.
|
||
|
|
|
||
|
|
-qcom,iova-width: The maximum number of bits that a TBU can support for IOVAs.
|
||
|
|
|
||
|
|
** TBU/QTB optional properties:
|
||
|
|
|
||
|
|
-qcom,opt-out-tbu-halting:
|
||
|
|
Allow certain TBUs to opt-out from being halted for the
|
||
|
|
ATOS operation to proceed. Halting certain TBUs would cause
|
||
|
|
considerable impact to the system such as deadlocks on demand.
|
||
|
|
Such TBUs can be opted out to be halted from software.
|
||
|
|
|
||
|
|
** QTB required properties:
|
||
|
|
-interconnects:
|
||
|
|
The interconnect path to vote for prior to accessing the QTB
|
||
|
|
registers.
|
||
|
|
|
||
|
|
-qcom,num-qtb-ports:
|
||
|
|
Specifies the number of ports that a QTB has for incoming
|
||
|
|
transactions.
|
||
|
|
|
||
|
|
** QTB optional properties:
|
||
|
|
|
||
|
|
-qcom,no-qtb-atos-halt:
|
||
|
|
Specifies that a TBU does not need to be halted for performing
|
||
|
|
ATOS debugging.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
TBU:
|
||
|
|
|
||
|
|
smmu {
|
||
|
|
compatible = "qcom,qsmmu-v500";
|
||
|
|
tbu@0x1000 {
|
||
|
|
compatible = "qcom,qsmmuv500-tbu";
|
||
|
|
reg = <0x1000 0x1000>;
|
||
|
|
qcom,stream-id-range = <0x800 0x400>;
|
||
|
|
qcom,iova-width = <36>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
QTB:
|
||
|
|
|
||
|
|
smmu {
|
||
|
|
compatible = "qcom,qsmmu-v500";
|
||
|
|
qtb@0x1000 {
|
||
|
|
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
||
|
|
regs = <0x1000 0x1000>;
|
||
|
|
qcom,stream-id-range = <0x800 0x400>;
|
||
|
|
qcom,iova-width = <36>;
|
||
|
|
interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>;
|
||
|
|
qcom,num-qtb-ports = <1>;
|
||
|
|
};
|
||
|
|
};
|