1009 lines
35 KiB
Text
1009 lines
35 KiB
Text
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#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
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#include <dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h>
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 138 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "noc_aggr_clk",
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"noc_aggr_north_clk", "noc_aggr_south_clk",
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"noc_sys_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
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qcom,host-poweroff-in-pm-suspend;
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status = "disabled";
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xd93c>;
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iommus = <&apps_smmu 0x0820 0x0>;
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qcom,iommu-dma = "bypass";
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interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy0>;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,ssp-u3-u0-quirk;
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snps,is-utmi-l1-suspend;
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snps,usb2-gadget-lpm-disable;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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dr_mode = "otg";
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usb-role-switch;
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@88e5000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x088e5000 0x120>;
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reg-names = "hsusb_phy_base";
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vdd-supply = <&L5A0>;
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vdda18-supply = <&L7A0>;
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vdda33-supply = <&L13A0>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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clocks = <&dummycc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq =
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<0x63 0x6c /* override_x0 */
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0xC8 0x70 /* override_x1 */
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0x17 0x74>; /* override x2 */
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status = "disabled";
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};
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/* Primary USB port related USB4-USB3-DP PHY */
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usb_qmp_dp_phy0: ssphy@88eb000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88eb000 0x4000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&L5A0>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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qcom,vdd-max-load-uA = <47000>;
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core-supply = <&L3A0>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
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<&dummycc RPMH_CXO_CLK>,
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<&gcc GCC_USB4_EUD_CLKREF_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
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"pipe_clk_ext_src", "ref_clk_src",
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"ref_clk", "com_aux_clk";
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resets = <&gcc GCC_USB4_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "global_phy_reset", "phy_reset";
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qcom,qmp-phy-reg-offset =
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<USB3_PCS_PCS_STATUS1
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USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL
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USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
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USB3_PCS_POWER_DOWN_CONTROL
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USB3_PCS_SW_RESET
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USB3_PCS_START_CONTROL
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0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
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USB43DP_COM_POWER_DOWN_CTRL
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USB43DP_COM_SW_RESET
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USB43DP_COM_RESET_OVRD_CTRL1
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USB43DP_COM_PHY_MODE_CTRL
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USB43DP_COM_TYPEC_CTRL
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USB3_PCS_CLAMP_ENABLE
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USB43DP_COM_TYPEC_STATUS>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value> */
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<USB3_QSERDES_PLL_SSC_EN_CENTER 0x01
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USB3_QSERDES_PLL_SSC_PER1 0x31
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USB3_QSERDES_PLL_SSC_PER2 0x01
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USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0xFD
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USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x0D
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USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0xFD
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USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x0D
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USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x0A
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USB3_QSERDES_PLL_CP_CTRL_MODE0 0x02
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USB3_QSERDES_PLL_CP_CTRL_MODE1 0x02
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USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x16
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USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x16
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USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x36
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USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x36
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USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1A
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USB3_QSERDES_PLL_LOCK_CMP_EN 0x04
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USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x14
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USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x34
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USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x34
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USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x82
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USB3_QSERDES_PLL_DEC_START_MODE0 0x04
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USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x01
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USB3_QSERDES_PLL_DEC_START_MODE1 0x04
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USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x01
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USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x55
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USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0xD5
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USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x05
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USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x55
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USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0xD5
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USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x05
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USB3_QSERDES_PLL_VCO_TUNE_MAP 0x02
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USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0xD4
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USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x00
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USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0xD4
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USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x00
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USB3_QSERDES_PLL_HSCLK_SEL 0x13
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USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x00
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USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x0A
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USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x04
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USB3_QSERDES_PLL_CORE_CLK_EN 0x60
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USB3_QSERDES_PLL_CMN_CONFIG 0x76
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USB3_QSERDES_PLL_PLL_IVCO 0xFF
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USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20
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USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20
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USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x00
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USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x01
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USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x0A
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USB43DP_QSERDES_TXA_LANE_MODE_1 0x05
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USB43DP_QSERDES_TXA_LANE_MODE_2 0xC2
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USB43DP_QSERDES_TXA_LANE_MODE_3 0x10
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USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
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USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0A
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USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x04
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USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
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USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x00
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0xD2
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0xD2
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0xDB
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x21
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x3F
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x80
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x45
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USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x00
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x6B
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x63
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0xB6
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x23
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x35
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x30
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x8E
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USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x00
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USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x00
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USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x80
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USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x1B
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USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
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USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x15
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USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0A
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USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x7C
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USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x00
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USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x0D
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USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x00
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USB43DP_QSERDES_RXA_DFE_3 0x45
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USB43DP_QSERDES_RXA_GM_CAL 0x09
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USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x09
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USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x05
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USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x3F
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USB43DP_QSERDES_TXB_LANE_MODE_1 0x05
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USB43DP_QSERDES_TXB_LANE_MODE_2 0xC2
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USB43DP_QSERDES_TXB_LANE_MODE_3 0x10
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USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
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USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A
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USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x04
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USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
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USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x00
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0xD2
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0xD2
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0xDB
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x21
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x3F
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x80
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x45
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USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x00
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x6B
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x63
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0xB6
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x23
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x35
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x30
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x8E
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USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x00
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USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x00
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USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x80
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USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x1B
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USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
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USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x15
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USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0A
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USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x7C
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USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x00
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USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0D
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USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x00
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USB43DP_QSERDES_RXB_DFE_3 0x45
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USB43DP_QSERDES_RXB_GM_CAL 0x09
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USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x09
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USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x05
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USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x3F
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USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
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|
|
USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG1 0xD0
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG2 0x07
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG3 0x20
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG6 0x13
|
||
|
|
USB3_PCS_REFGEN_REQ_CONFIG1 0x21
|
||
|
|
USB3_PCS_RX_SIGDET_LVL 0xAA
|
||
|
|
USB3_PCS_RX_CONFIG 0x0A
|
||
|
|
USB3_PCS_ALIGN_DETECT_CONFIG1 0x88
|
||
|
|
USB3_PCS_ALIGN_DETECT_CONFIG2 0x13
|
||
|
|
USB3_PCS_PCS_TX_RX_CONFIG 0x0C
|
||
|
|
USB3_PCS_EQ_CONFIG1 0x4B
|
||
|
|
USB3_PCS_EQ_CONFIG5 0x10
|
||
|
|
USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
|
||
|
|
USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_nop_phy: usb_nop_phy {
|
||
|
|
compatible = "usb-nop-xceiv";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb1: ssusb@a800000 {
|
||
|
|
compatible = "qcom,dwc-usb3-msm";
|
||
|
|
reg = <0xa800000 0x100000>;
|
||
|
|
reg-names = "core_base";
|
||
|
|
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
dma-ranges;
|
||
|
|
|
||
|
|
interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
|
||
|
|
|
||
|
|
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||
|
|
"ss_phy_irq", "dm_hs_phy_irq";
|
||
|
|
qcom,use-pdc-interrupts;
|
||
|
|
|
||
|
|
USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
|
||
|
|
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||
|
|
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
|
||
|
|
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
|
||
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||
|
|
"utmi_clk", "sleep_clk", "noc_aggr_clk",
|
||
|
|
"noc_aggr_north_clk", "noc_aggr_south_clk",
|
||
|
|
"noc_sys_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||
|
|
reset-names = "core_reset";
|
||
|
|
|
||
|
|
qcom,core-clk-rate = <200000000>;
|
||
|
|
qcom,core-clk-rate-hs = <66666667>;
|
||
|
|
|
||
|
|
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
|
||
|
|
qcom,host-poweroff-in-pm-suspend;
|
||
|
|
qcom,default-mode-host;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
dwc3@a800000 {
|
||
|
|
compatible = "snps,dwc3";
|
||
|
|
reg = <0xa800000 0xd93c>;
|
||
|
|
iommus = <&apps_smmu 0x0860 0x0>;
|
||
|
|
qcom,iommu-dma = "bypass";
|
||
|
|
interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
usb-phy = <&usb2_phy1>, <&usb_qmp_dp_phy1>;
|
||
|
|
snps,disable-clk-gating;
|
||
|
|
snps,has-lpm-erratum;
|
||
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
||
|
|
snps,ssp-u3-u0-quirk;
|
||
|
|
snps,is-utmi-l1-suspend;
|
||
|
|
snps,dis-u1-entry-quirk;
|
||
|
|
snps,dis-u2-entry-quirk;
|
||
|
|
snps,usb2-gadget-lpm-disable;
|
||
|
|
tx-fifo-resize;
|
||
|
|
maximum-speed = "super-speed-plus";
|
||
|
|
dr_mode = "otg";
|
||
|
|
usb-role-switch;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Secondary USB port related High Speed PHY */
|
||
|
|
usb2_phy1: hsphy@8902000 {
|
||
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
||
|
|
reg = <0x08902000 0x120>;
|
||
|
|
reg-names = "hsusb_phy_base";
|
||
|
|
|
||
|
|
vdd-supply = <&L1C0>;
|
||
|
|
vdda18-supply = <&L7C0>;
|
||
|
|
vdda33-supply = <&L2C0>;
|
||
|
|
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
|
||
|
|
clocks = <&dummycc RPMH_CXO_CLK>;
|
||
|
|
clock-names = "ref_clk_src";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
|
||
|
|
reset-names = "phy_reset";
|
||
|
|
qcom,param-override-seq =
|
||
|
|
<0x63 0x6c /* override_x0 */
|
||
|
|
0xC8 0x70 /* override_x1 */
|
||
|
|
0x17 0x74>; /* override x2 */
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Secondary USB port related USB4-USB3-DP PHY */
|
||
|
|
usb_qmp_dp_phy1: ssphy@8903000 {
|
||
|
|
compatible = "qcom,usb-ssphy-qmp-dp-combo";
|
||
|
|
reg = <0x8903000 0x4000>;
|
||
|
|
reg-names = "qmp_phy_base";
|
||
|
|
|
||
|
|
vdd-supply = <&L1C0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
qcom,vdd-max-load-uA = <47000>;
|
||
|
|
core-supply = <&L4C0>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
||
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
|
||
|
|
<&usb3_uni_phy_sec_gcc_usb30_pipe_clk>,
|
||
|
|
<&dummycc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_USB4_CLKREF_CLK>,
|
||
|
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
||
|
|
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
|
||
|
|
"pipe_clk_ext_src", "ref_clk_src",
|
||
|
|
"ref_clk", "com_aux_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>,
|
||
|
|
<&gcc GCC_USB3_PHY_SEC_BCR>;
|
||
|
|
reset-names = "global_phy_reset", "phy_reset";
|
||
|
|
|
||
|
|
qcom,qmp-phy-reg-offset =
|
||
|
|
<USB3_PCS_PCS_STATUS1
|
||
|
|
USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
||
|
|
USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
||
|
|
USB3_PCS_POWER_DOWN_CONTROL
|
||
|
|
USB3_PCS_SW_RESET
|
||
|
|
USB3_PCS_START_CONTROL
|
||
|
|
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
|
||
|
|
USB43DP_COM_POWER_DOWN_CTRL
|
||
|
|
USB43DP_COM_SW_RESET
|
||
|
|
USB43DP_COM_RESET_OVRD_CTRL1
|
||
|
|
USB43DP_COM_PHY_MODE_CTRL
|
||
|
|
USB43DP_COM_TYPEC_CTRL
|
||
|
|
USB3_PCS_CLAMP_ENABLE
|
||
|
|
USB43DP_COM_TYPEC_STATUS>;
|
||
|
|
|
||
|
|
qcom,qmp-phy-init-seq =
|
||
|
|
/* <reg_offset, value, delay> */
|
||
|
|
<USB3_QSERDES_PLL_SSC_EN_CENTER 0x01
|
||
|
|
USB3_QSERDES_PLL_SSC_PER1 0x31
|
||
|
|
USB3_QSERDES_PLL_SSC_PER2 0x01
|
||
|
|
USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0xFD
|
||
|
|
USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x0D
|
||
|
|
USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0xFD
|
||
|
|
USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x0D
|
||
|
|
USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x0A
|
||
|
|
USB3_QSERDES_PLL_CP_CTRL_MODE0 0x02
|
||
|
|
USB3_QSERDES_PLL_CP_CTRL_MODE1 0x02
|
||
|
|
USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x16
|
||
|
|
USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x16
|
||
|
|
USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x36
|
||
|
|
USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x36
|
||
|
|
USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1A
|
||
|
|
USB3_QSERDES_PLL_LOCK_CMP_EN 0x04
|
||
|
|
USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x14
|
||
|
|
USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x34
|
||
|
|
USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x34
|
||
|
|
USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x82
|
||
|
|
USB3_QSERDES_PLL_DEC_START_MODE0 0x04
|
||
|
|
USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x01
|
||
|
|
USB3_QSERDES_PLL_DEC_START_MODE1 0x04
|
||
|
|
USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x01
|
||
|
|
USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x55
|
||
|
|
USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0xD5
|
||
|
|
USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x05
|
||
|
|
USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x55
|
||
|
|
USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0xD5
|
||
|
|
USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x05
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE_MAP 0x02
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0xD4
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x00
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0xD4
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x00
|
||
|
|
USB3_QSERDES_PLL_HSCLK_SEL 0x13
|
||
|
|
USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x00
|
||
|
|
USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x0A
|
||
|
|
USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x04
|
||
|
|
USB3_QSERDES_PLL_CORE_CLK_EN 0x60
|
||
|
|
USB3_QSERDES_PLL_CMN_CONFIG 0x76
|
||
|
|
USB3_QSERDES_PLL_PLL_IVCO 0xFF
|
||
|
|
USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20
|
||
|
|
USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x00
|
||
|
|
USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x01
|
||
|
|
USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x0A
|
||
|
|
USB43DP_QSERDES_TXA_LANE_MODE_1 0x05
|
||
|
|
USB43DP_QSERDES_TXA_LANE_MODE_2 0xC2
|
||
|
|
USB43DP_QSERDES_TXA_LANE_MODE_3 0x10
|
||
|
|
USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
|
||
|
|
USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0A
|
||
|
|
USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x04
|
||
|
|
USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
|
||
|
|
USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x00
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0xD2
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0xD2
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0xDB
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x21
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x3F
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x80
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x45
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x00
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x6B
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x63
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0xB6
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x23
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x35
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x30
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x8E
|
||
|
|
USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x00
|
||
|
|
USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x00
|
||
|
|
USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x80
|
||
|
|
USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x1B
|
||
|
|
USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
|
||
|
|
USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x15
|
||
|
|
USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0A
|
||
|
|
USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x7C
|
||
|
|
USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x00
|
||
|
|
USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x0D
|
||
|
|
USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x00
|
||
|
|
USB43DP_QSERDES_RXA_DFE_3 0x45
|
||
|
|
USB43DP_QSERDES_RXA_GM_CAL 0x09
|
||
|
|
USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x09
|
||
|
|
USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x05
|
||
|
|
USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x3F
|
||
|
|
USB43DP_QSERDES_TXB_LANE_MODE_1 0x05
|
||
|
|
USB43DP_QSERDES_TXB_LANE_MODE_2 0xC2
|
||
|
|
USB43DP_QSERDES_TXB_LANE_MODE_3 0x10
|
||
|
|
USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
|
||
|
|
USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A
|
||
|
|
USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x04
|
||
|
|
USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
|
||
|
|
USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x00
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0xD2
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0xD2
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0xDB
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x21
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x3F
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x80
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x45
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x00
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x6B
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x63
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0xB6
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x23
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x35
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x30
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x8E
|
||
|
|
USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x00
|
||
|
|
USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x00
|
||
|
|
USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x80
|
||
|
|
USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x1B
|
||
|
|
USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
|
||
|
|
USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x15
|
||
|
|
USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0A
|
||
|
|
USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x7C
|
||
|
|
USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x00
|
||
|
|
USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0D
|
||
|
|
USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x00
|
||
|
|
USB43DP_QSERDES_RXB_DFE_3 0x45
|
||
|
|
USB43DP_QSERDES_RXB_GM_CAL 0x09
|
||
|
|
USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x09
|
||
|
|
USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x05
|
||
|
|
USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x3F
|
||
|
|
USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
|
||
|
|
USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG1 0xD0
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG2 0x07
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG3 0x20
|
||
|
|
USB3_PCS_LOCK_DETECT_CONFIG6 0x13
|
||
|
|
USB3_PCS_REFGEN_REQ_CONFIG1 0x21
|
||
|
|
USB3_PCS_RX_SIGDET_LVL 0xAA
|
||
|
|
USB3_PCS_RX_CONFIG 0x0A
|
||
|
|
USB3_PCS_ALIGN_DETECT_CONFIG1 0x88
|
||
|
|
USB3_PCS_ALIGN_DETECT_CONFIG2 0x13
|
||
|
|
USB3_PCS_PCS_TX_RX_CONFIG 0x0C
|
||
|
|
USB3_PCS_EQ_CONFIG1 0x4B
|
||
|
|
USB3_PCS_EQ_CONFIG5 0x10
|
||
|
|
USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
|
||
|
|
USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port related controller */
|
||
|
|
usb2: ssusb@a400000 {
|
||
|
|
compatible = "qcom,dwc-usb3-msm";
|
||
|
|
reg = <0xa400000 0x100000>;
|
||
|
|
reg-names = "core_base";
|
||
|
|
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
dma-ranges;
|
||
|
|
|
||
|
|
interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 126 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 129 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 128 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 131 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 130 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 133 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 132 IRQ_TYPE_EDGE_RISING>,
|
||
|
|
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
|
||
|
|
"dp_hs_phy_irq1", "dm_hs_phy_irq1",
|
||
|
|
"dp_hs_phy_irq2", "dm_hs_phy_irq2",
|
||
|
|
"dp_hs_phy_irq3", "dm_hs_phy_irq3",
|
||
|
|
"ss_phy_irq", "ss_phy_irq1";
|
||
|
|
qcom,use-pdc-interrupts;
|
||
|
|
|
||
|
|
USB3_GDSC-supply = <&gcc_usb30_mp_gdsc>;
|
||
|
|
clocks = <&gcc GCC_USB30_MP_MASTER_CLK>,
|
||
|
|
<&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
|
||
|
|
<&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
|
||
|
|
<&gcc GCC_USB30_MP_SLEEP_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
|
||
|
|
<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
|
||
|
|
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
|
||
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||
|
|
"utmi_clk", "sleep_clk", "noc_aggr_clk",
|
||
|
|
"noc_aggr_north_clk", "noc_aggr_south_clk",
|
||
|
|
"noc_sys_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB30_MP_BCR>;
|
||
|
|
reset-names = "core_reset";
|
||
|
|
|
||
|
|
qcom,core-clk-rate = <200000000>;
|
||
|
|
qcom,host-poweroff-in-pm-suspend;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
dwc3@a400000 {
|
||
|
|
compatible = "snps,dwc3";
|
||
|
|
reg = <0xa400000 0xd93c>;
|
||
|
|
iommus = <&apps_smmu 0x0800 0x0>;
|
||
|
|
qcom,iommu-dma = "bypass";
|
||
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>,
|
||
|
|
<&usb2_phy3>, <&usb_qmp_phy1>,
|
||
|
|
<&usb2_phy4>, <&usb_nop_phy>,
|
||
|
|
<&usb2_phy5>, <&usb_nop_phy>;
|
||
|
|
snps,disable-clk-gating;
|
||
|
|
snps,has-lpm-erratum;
|
||
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
||
|
|
snps,ssp-u3-u0-quirk;
|
||
|
|
snps,is-utmi-l1-suspend;
|
||
|
|
snps,dis_u3_susphy_quirk;
|
||
|
|
maximum-speed = "super-speed-plus";
|
||
|
|
dr_mode = "host";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port 0 related High Speed PHY */
|
||
|
|
usb2_phy2: hsphy@88e7000 {
|
||
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
||
|
|
reg = <0x88e7000 0x120>;
|
||
|
|
reg-names = "hsusb_phy_base";
|
||
|
|
|
||
|
|
vdd-supply = <&L5A0>;
|
||
|
|
vdda18-supply = <&L7G0>;
|
||
|
|
vdda33-supply = <&L13A0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
|
||
|
|
clock-names = "ref_clk_src";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
|
||
|
|
reset-names = "phy_reset";
|
||
|
|
qcom,param-override-seq =
|
||
|
|
<0x63 0x6c /* override_x0 */
|
||
|
|
0xC8 0x70 /* override_x1 */
|
||
|
|
0x17 0x74>; /* override x2 */
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port 0 related QMP PHY */
|
||
|
|
usb_qmp_phy0: ssphy@88ef000 {
|
||
|
|
compatible = "qcom,usb-ssphy-qmp-v2";
|
||
|
|
reg = <0x88ef000 0x2000>,
|
||
|
|
<0x088ef28c 0x4>;
|
||
|
|
reg-names = "qmp_phy_base",
|
||
|
|
"pcs_clamp_enable_reg";
|
||
|
|
|
||
|
|
vdd-supply = <&L5A0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
qcom,vdd-max-load-uA = <47000>;
|
||
|
|
core-supply = <&L3A0>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP_PHY_PIPE_0_CLK_SRC>,
|
||
|
|
<&usb3_uni_phy_mp_gcc_usb30_pipe_0_clk>,
|
||
|
|
<&dummycc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP0_CLKREF_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
|
||
|
|
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
|
||
|
|
"pipe_clk_ext_src", "ref_clk_src",
|
||
|
|
"ref_clk", "com_aux_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
|
||
|
|
<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
|
||
|
|
reset-names = "phy_reset", "phy_phy_reset";
|
||
|
|
|
||
|
|
qcom,qmp-phy-reg-offset =
|
||
|
|
<USB3_UNI_PCS_PCS_STATUS1
|
||
|
|
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
||
|
|
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
||
|
|
USB3_UNI_PCS_POWER_DOWN_CONTROL
|
||
|
|
USB3_UNI_PCS_SW_RESET
|
||
|
|
USB3_UNI_PCS_START_CONTROL>;
|
||
|
|
|
||
|
|
qcom,qmp-phy-init-seq =
|
||
|
|
/* <reg_offset, value, delay> */
|
||
|
|
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
|
||
|
|
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
|
||
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
|
||
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
|
||
|
|
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
|
||
|
|
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
|
||
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
|
||
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_PER1 0x31
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_PER2 0x01
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A
|
||
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
|
||
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F
|
||
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F
|
||
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A
|
||
|
|
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
|
||
|
|
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
|
||
|
|
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
|
||
|
|
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E
|
||
|
|
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05
|
||
|
|
USB3_UNI_QSERDES_RX_GM_CAL 0x00
|
||
|
|
USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F
|
||
|
|
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21
|
||
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
|
||
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
|
||
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
|
||
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
||
|
|
USB3_UNI_PCS_RX_SIGDET_LVL 0xAA
|
||
|
|
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C
|
||
|
|
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
|
||
|
|
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
|
||
|
|
USB3_UNI_PCS_CDR_RESET_TIME 0x0A
|
||
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
|
||
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
|
||
|
|
USB3_UNI_PCS_EQ_CONFIG1 0x4B
|
||
|
|
USB3_UNI_PCS_EQ_CONFIG5 0x10
|
||
|
|
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port 1 related High Speed PHY */
|
||
|
|
usb2_phy3: hsphy@88e8000 {
|
||
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
||
|
|
reg = <0x88e8000 0x120>;
|
||
|
|
reg-names = "hsusb_phy_base";
|
||
|
|
|
||
|
|
vdd-supply = <&L5A0>;
|
||
|
|
vdda18-supply = <&L7G0>;
|
||
|
|
vdda33-supply = <&L13A0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
|
||
|
|
clock-names = "ref_clk_src";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
|
||
|
|
reset-names = "phy_reset";
|
||
|
|
qcom,param-override-seq =
|
||
|
|
<0x63 0x6c /* override_x0 */
|
||
|
|
0xC8 0x70 /* override_x1 */
|
||
|
|
0x17 0x74>; /* override x2 */
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port 1 related QMP PHY */
|
||
|
|
usb_qmp_phy1: ssphy@88f1000 {
|
||
|
|
compatible = "qcom,usb-ssphy-qmp-v2";
|
||
|
|
reg = <0x88f1000 0x2000>,
|
||
|
|
<0x088f128c 0x4>;
|
||
|
|
reg-names = "qmp_phy_base",
|
||
|
|
"pcs_clamp_enable_reg";
|
||
|
|
|
||
|
|
vdd-supply = <&L5A0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
qcom,vdd-max-load-uA = <47000>;
|
||
|
|
core-supply = <&L3A0>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP_PHY_PIPE_1_CLK_SRC>,
|
||
|
|
<&usb3_uni_phy_mp_gcc_usb30_pipe_1_clk>,
|
||
|
|
<&dummycc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP1_CLKREF_CLK>,
|
||
|
|
<&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
|
||
|
|
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
|
||
|
|
"pipe_clk_ext_src", "ref_clk_src",
|
||
|
|
"ref_clk", "com_aux_clk";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
|
||
|
|
<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
|
||
|
|
reset-names = "phy_reset", "phy_phy_reset";
|
||
|
|
|
||
|
|
qcom,qmp-phy-reg-offset =
|
||
|
|
<USB3_UNI_PCS_PCS_STATUS1
|
||
|
|
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
||
|
|
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
||
|
|
USB3_UNI_PCS_POWER_DOWN_CONTROL
|
||
|
|
USB3_UNI_PCS_SW_RESET
|
||
|
|
USB3_UNI_PCS_START_CONTROL>;
|
||
|
|
|
||
|
|
qcom,qmp-phy-init-seq =
|
||
|
|
/* <reg_offset, value, delay> */
|
||
|
|
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
|
||
|
|
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
|
||
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
|
||
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
|
||
|
|
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
|
||
|
|
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
|
||
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
|
||
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
|
||
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
|
||
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
|
||
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
|
||
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_PER1 0x31
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_PER2 0x01
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
|
||
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
|
||
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24
|
||
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A
|
||
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
|
||
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F
|
||
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F
|
||
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A
|
||
|
|
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
|
||
|
|
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
|
||
|
|
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
|
||
|
|
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E
|
||
|
|
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
|
||
|
|
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05
|
||
|
|
USB3_UNI_QSERDES_RX_GM_CAL 0x00
|
||
|
|
USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F
|
||
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F
|
||
|
|
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21
|
||
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
|
||
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
|
||
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
|
||
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
|
||
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
||
|
|
USB3_UNI_PCS_RX_SIGDET_LVL 0xAA
|
||
|
|
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C
|
||
|
|
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
|
||
|
|
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
|
||
|
|
USB3_UNI_PCS_CDR_RESET_TIME 0x0A
|
||
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
|
||
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
|
||
|
|
USB3_UNI_PCS_EQ_CONFIG1 0x4B
|
||
|
|
USB3_UNI_PCS_EQ_CONFIG5 0x10
|
||
|
|
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21>;
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port 2 related High Speed PHY */
|
||
|
|
usb2_phy4: hsphy@88e9000 {
|
||
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
||
|
|
reg = <0x88e9000 0x120>;
|
||
|
|
reg-names = "hsusb_phy_base";
|
||
|
|
|
||
|
|
vdd-supply = <&L5A0>;
|
||
|
|
vdda18-supply = <&L7G0>;
|
||
|
|
vdda33-supply = <&L13A0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
|
||
|
|
clock-names = "ref_clk_src";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
|
||
|
|
reset-names = "phy_reset";
|
||
|
|
qcom,param-override-seq =
|
||
|
|
<0x63 0x6c /* override_x0 */
|
||
|
|
0xC8 0x70 /* override_x1 */
|
||
|
|
0x17 0x74>; /* override x2 */
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Tertiary USB port 3 related High Speed PHY */
|
||
|
|
usb2_phy5: hsphy@88ea000 {
|
||
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
||
|
|
reg = <0x88ea000 0x120>;
|
||
|
|
reg-names = "hsusb_phy_base";
|
||
|
|
|
||
|
|
vdd-supply = <&L5A0>;
|
||
|
|
vdda18-supply = <&L7G0>;
|
||
|
|
vdda33-supply = <&L13A0>;
|
||
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
|
||
|
|
clock-names = "ref_clk_src";
|
||
|
|
|
||
|
|
resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
|
||
|
|
reset-names = "phy_reset";
|
||
|
|
qcom,param-override-seq =
|
||
|
|
<0x63 0x6c /* override_x0 */
|
||
|
|
0xC8 0x70 /* override_x1 */
|
||
|
|
0x17 0x74>; /* override x2 */
|
||
|
|
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|