685 lines
15 KiB
Text
685 lines
15 KiB
Text
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&msm_gpu {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok";
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reg = <0x5900000 0x90000>,
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<0x5961000 0x800>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";
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interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,gpu-model = "Adreno610v1";
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qcom,chipid = <0x06010000>;
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qcom,initial-pwrlevel = <6>;
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qcom,ubwc-mode = <1>;
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qcom,min-access-length = <64>;
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/* base addr, size */
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qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
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#cooling-cells = <2>;
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clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_BIMC_GPU_AXI_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&rpmcc RPM_SMD_QDSS_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
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clock-names = "core_clk",
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"rbbmtimer_clk",
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"iface_clk",
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"ahb_clk",
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"mem_clk",
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"gmu_clk",
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"smmu_vote",
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"apb_pclk",
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"gpu_cc_ahb",
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"gcc_gpu_memnoc_gfx",
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"gpu_cc_hlos1_vote_gpu_smmu",
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"gcc_gpu_snoc_dvm_gfx";
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interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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qcom,bus-table-ddr =
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<MHZ_TO_KBPS(0, 8)>, /* index=0 */
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<MHZ_TO_KBPS(100, 8)>, /* index=1 */
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<MHZ_TO_KBPS(200, 8)>, /* index=2 */
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<MHZ_TO_KBPS(300, 8)>, /* index=3 */
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<MHZ_TO_KBPS(451, 8)>, /* index=4 */
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<MHZ_TO_KBPS(547, 8)>, /* index=5 */
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<MHZ_TO_KBPS(681, 8)>, /* index=6 */
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<MHZ_TO_KBPS(768, 8)>, /* index=7 */
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<MHZ_TO_KBPS(1017, 8)>, /* index=8 */
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<MHZ_TO_KBPS(1353, 8)>, /* index=9 */
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<MHZ_TO_KBPS(1555, 8)>, /* index=10 */
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<MHZ_TO_KBPS(1804, 8)>; /* index=11 */
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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/* CPU latency parameter */
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qcom,pm-qos-active-latency = <422>;
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qcom,pm-qos-wakeup-latency = <422>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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/* Context aware jump target power level */
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qcom,ca-target-pwrlevel = <5>;
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nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
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nvmem-cell-names = "speed_bin", "gaming_bin";
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qcom,gpu-cx-ipeak {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-cx-ipeak";
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qcom,gpu-cx-ipeak@0 {
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qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>;
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qcom,gpu-cx-ipeak-freq = <950000000>;
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};
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qcom,gpu-cx-ipeak@1 {
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qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;
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qcom,gpu-cx-ipeak-freq = <900000000>;
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};
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};
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/* ZAP Shader memory */
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zap-shader {
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memory-region = <&pil_gpu_mem>;
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};
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/* GPU Mempool configuration for low memory SKUs */
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qcom,gpu-mempools-lowmem {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools-lowmem";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-allocate;
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qcom,mempool-max-pages = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-allocate;
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qcom,mempool-max-pages = <32>;
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};
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};
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/*
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* Speed-bin zero is default speed bin.
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* For rest of the speed bins, speed-bin value
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* is calculated as FMAX/4.8 MHz round up to zero
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* decimal places plus two margin to account for
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* clock jitters.
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*/
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <6>;
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qcom,ca-target-pwrlevel = <5>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <980000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <900000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <820000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <745000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <600000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <8>;
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qcom,bus-max = <9>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <320000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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/* XO */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <206>;
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qcom,initial-pwrlevel = <6>;
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qcom,ca-target-pwrlevel = <5>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <980000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <900000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <820000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <745000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <600000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <8>;
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qcom,bus-max = <9>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <320000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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/* XO */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <200>;
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qcom,initial-pwrlevel = <6>;
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qcom,ca-target-pwrlevel = <5>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <950000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <900000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <820000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <745000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <600000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <8>;
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qcom,bus-max = <9>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <320000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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/* XO */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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qcom,gpu-pwrlevels-3 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <157>;
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qcom,initial-pwrlevel = <3>;
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qcom,ca-target-pwrlevel = <2>;
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/* NOM */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <745000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <600000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <8>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
/* LOW SVS */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <320000000>;
|
|
qcom,bus-freq = <4>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <127>;
|
|
|
|
qcom,initial-pwrlevel = <2>;
|
|
qcom,ca-target-pwrlevel = <1>;
|
|
|
|
/* SVS_L1 */
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <600000000>;
|
|
qcom,bus-freq = <11>;
|
|
qcom,bus-min = <8>;
|
|
qcom,bus-max = <11>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
/* SVS */
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <465000000>;
|
|
qcom,bus-freq = <7>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
/* LOW SVS */
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <320000000>;
|
|
qcom,bus-freq = <4>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
|
|
&soc {
|
|
gpu_opp_table: gpu-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-980000000 {
|
|
opp-hz = /bits/ 64 <980000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
|
|
opp-950000000 {
|
|
opp-hz = /bits/ 64 <950000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
|
|
opp-900000000 {
|
|
opp-hz = /bits/ 64 <900000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
opp-820000000 {
|
|
opp-hz = /bits/ 64 <820000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
opp-745000000 {
|
|
opp-hz = /bits/ 64 <745000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
opp-600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
opp-465000000 {
|
|
opp-hz = /bits/ 64 <465000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
opp-320000000 {
|
|
opp-hz = /bits/ 64 <320000000>;
|
|
opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
};
|
|
|
|
gpu_bw_tbl: gpu-bw-tbl {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
|
|
|
|
opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */
|
|
|
|
opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */
|
|
|
|
opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */
|
|
|
|
opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */
|
|
|
|
opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */
|
|
|
|
opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */
|
|
|
|
opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */
|
|
|
|
opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */
|
|
|
|
opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */
|
|
|
|
opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */
|
|
|
|
opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */
|
|
};
|
|
|
|
gpubw: qcom,gpubw {
|
|
compatible = "qcom,devbw";
|
|
governor = "bw_vbif";
|
|
qcom,src-dst-ports = <26 512>;
|
|
operating-points-v2 = <&gpu_bw_tbl>;
|
|
};
|
|
|
|
kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
|
|
reg = <0x59a0000 0x10000>;
|
|
qcom,protect = <0xa0000 0x10000>;
|
|
|
|
vddcx-supply = <&gpu_cx_gdsc>;
|
|
qcom,retention;
|
|
qcom,hyp_secure_alloc;
|
|
|
|
gfx3d_user: gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_user";
|
|
iommus = <&kgsl_smmu 0 1>;
|
|
qcom,iommu-dma = "disabled";
|
|
qcom,gpu-offset = <0xa8000>;
|
|
};
|
|
|
|
gfx3d_secure: gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_secure";
|
|
iommus = <&kgsl_smmu 2 0>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
};
|
|
};
|