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msm: ipa: Fix considering prefetch buf size when mapping

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IPA HW tries to prefetch 128 Bytes of additional memory when
dealing with filter/routing tables. This can result in overflowing
of memory if we map only the required size. Make changes to
consider prefetch memory when allocating routing/filter tables.

Change-Id: Id72e4df285a4683dddebb18d98bb9c4dd9667eeb
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
This commit is contained in:
Chaitanya Pratapa 2020-03-22 23:56:47 -07:00 • committed by Mohit Sharma
commit 01a1446065
5 changed files with 22 additions and 0 deletions
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3
drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
View file

@ -227,6 +227,9 @@ static int ipa_translate_flt_tbl_to_hw_fmt(enum ipa_ip_type ip,
/* only body (no header) */
tbl_mem.size = tbl->sz[rlt] -
ipahal_get_hw_tbl_hdr_width();
/* Add prefetech buf size. */
tbl_mem.size +=
ipahal_get_hw_prefetch_buf_size();
if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) {
IPAERR("fail to alloc sys tbl of size %d\n",
tbl_mem.size);

3
drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
View file

@ -169,6 +169,9 @@ static int ipa_translate_rt_tbl_to_hw_fmt(enum ipa_ip_type ip,
/* only body (no header) */
tbl_mem.size = tbl->sz[rlt] -
ipahal_get_hw_tbl_hdr_width();
/* Add prefetech buf size. */
tbl_mem.size +=
ipahal_get_hw_prefetch_buf_size();
if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) {
IPAERR_RL("fail to alloc sys tbl of size %d\n",
tbl_mem.size);

12
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
View file

@ -44,6 +44,7 @@
* @flt_parse_hw_rule: Parse flt rule read from H/W
* @eq_bitfield: Array of the bit fields of the support equations.
* 0xFF means the equation is not supported
* @prefetech_buf_size: Prefetch buf size;
*/
struct ipahal_fltrt_obj {
bool support_hash;
@ -73,6 +74,7 @@ struct ipahal_fltrt_obj {
int (*rt_parse_hw_rule)(u8 *addr, struct ipahal_rt_rule_entry *rule);
int (*flt_parse_hw_rule)(u8 *addr, struct ipahal_flt_rule_entry *rule);
u8 eq_bitfield[IPA_EQ_MAX];
u32 prefetech_buf_size;
};
@ -654,6 +656,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = {
[IPA_IS_FRAG] = 15,
[IPA_IS_PURE_ACK] = 0xFF,
},
IPA3_0_HW_RULE_PREFETCH_BUF_SIZE,
},
/* IPAv4 */
@ -699,6 +702,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = {
[IPA_IS_FRAG] = 15,
[IPA_IS_PURE_ACK] = 0xFF,
},
IPA3_0_HW_RULE_PREFETCH_BUF_SIZE,
},
/* IPAv4.2 */
@ -744,6 +748,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = {
[IPA_IS_FRAG] = 15,
[IPA_IS_PURE_ACK] = 0xFF,
},
IPA3_0_HW_RULE_PREFETCH_BUF_SIZE,
},
/* IPAv4.5 */
@ -789,6 +794,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = {
[IPA_IS_FRAG] = 15,
[IPA_IS_PURE_ACK] = 0,
},
IPA3_0_HW_RULE_PREFETCH_BUF_SIZE,
},
};
@ -3593,6 +3599,12 @@ u32 ipahal_get_lcl_tbl_addr_alignment(void)
return ipahal_fltrt_objs[ipahal_ctx->hw_type].lcladdr_alignment;
}
/* Get the H/W (flt/rt) prefetch buf size */
u32 ipahal_get_hw_prefetch_buf_size(void)
{
return ipahal_fltrt_objs[ipahal_ctx->hw_type].prefetech_buf_size;
}
/*
* Rule priority is used to distinguish rules order
* at the integrated table consisting from hashable and

3
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h
View file

@ -140,6 +140,9 @@ u32 ipahal_get_hw_tbl_hdr_width(void);
*/
u32 ipahal_get_lcl_tbl_addr_alignment(void);
/* Get the H/W (flt/rt) prefetch buf size */
u32 ipahal_get_hw_prefetch_buf_size(void);
/*
* Rule priority is used to distinguish rules order
* at the integrated table consisting from hashable and

1
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h
View file

@ -44,6 +44,7 @@ enum ipa_fltrt_equations {
#define IPA3_0_HW_TBL_ADDR_MASK (127)
#define IPA3_0_HW_RULE_BUF_SIZE (256)
#define IPA3_0_HW_RULE_START_ALIGNMENT (7)
#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (128)
/*