A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-10 14:19:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

drivers: llcc: Write to sub-cache register based on version

Browse source 
Configure the write sub-cache register based on the version, as
it's not supported by older targets.

Change-Id: Ifc3f2d4d66612d6dcc6070d3cbc3fce97202ccf3
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
[rananta@codeaurora.org: Resolved trivial merge conflicts]
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
This commit is contained in:
Rishabh Bhatnagar 2019-02-28 12:10:51 -08:00 • committed by Raghavendra Rao Ananta
commit 01ea45d72a
2 changed files with 17 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

14
drivers/soc/qcom/llcc-slice.c
View file

@ -263,12 +263,15 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
u32 sz;
u32 pcb = 0;
u32 cad = 0;
u32 wren = 0;
int ret = 0;
const struct llcc_slice_config *llcc_table;
struct llcc_slice_desc desc;
bool cap_based_alloc_and_pwr_collapse =
drv_data->cap_based_alloc_and_pwr_collapse;
uint32_t mask = ~0;
int v2_ver = of_device_is_compatible(pdev->dev.of_node,
"qcom,llcc-v2");
sz = drv_data->cfg_size;
llcc_table = drv_data->cfg;
@ -276,7 +279,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
/* Disable the Cache as Non-Cache override and enable
* the Non-Cache as Cache override
*/
if (of_device_is_compatible(pdev->dev.of_node, "qcom,llcc-v2")) {
if (v2_ver) {
ret = regmap_write(drv_data->bcast_regmap,
LLCC_TRP_C_AS_NC, 0);
if (ret)
@ -334,6 +337,15 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
if (ret)
return ret;
if (v2_ver) {
wren |= llcc_table[i].write_scid_en <<
llcc_table[i].slice_id;
ret = regmap_write(drv_data->bcast_regmap,
LLCC_TRP_WRSC_EN, wren);
if (ret)
return ret;
}
if (cap_based_alloc_and_pwr_collapse) {
cad |= llcc_table[i].dis_cap_alloc <<
llcc_table[i].slice_id;

6
include/linux/soc/qcom/llcc-qcom.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*
*/
@ -48,7 +48,8 @@ struct llcc_slice_desc {
* @res_ways: reserved ways associated with llcc slice
* @cache_mode: mode of the llcc slice
* @probe_target_ways: Probe only reserved and bonus ways on a cache miss
* @dis_cap_alloc: Disable capacity based allocation
* @dis_icap_alloc: Disable capacity based allocation
* @write_scid_en: Enables write cache support for a given scid.
* @retain_on_pc: Retain through power collapse
* @activate_on_init: activate the slice on init
*/
@ -63,6 +64,7 @@ struct llcc_slice_config {
u32 cache_mode;
u32 probe_target_ways;
bool dis_cap_alloc;
bool write_scid_en;
bool retain_on_pc;
bool activate_on_init;
};