mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 12:58:12 -04:00
Merge "defconfig: disable CONFIG_FORTIFY_SOURCE"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
0801ac3d8f
1000 changed files with 54321 additions and 49011 deletions
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@ -3002,10 +3002,10 @@
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65 = /dev/infiniband/issm1 Second InfiniBand IsSM device
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||||
...
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||||
127 = /dev/infiniband/issm63 63rd InfiniBand IsSM device
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||||
128 = /dev/infiniband/uverbs0 First InfiniBand verbs device
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||||
129 = /dev/infiniband/uverbs1 Second InfiniBand verbs device
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||||
192 = /dev/infiniband/uverbs0 First InfiniBand verbs device
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||||
193 = /dev/infiniband/uverbs1 Second InfiniBand verbs device
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||||
...
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||||
159 = /dev/infiniband/uverbs31 31st InfiniBand verbs device
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||||
223 = /dev/infiniband/uverbs31 31st InfiniBand verbs device
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||||
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||||
232 char Biometric Devices
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||||
0 = /dev/biometric/sensor0/fingerprint first fingerprint sensor on first device
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||||
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|||
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@ -5495,6 +5495,13 @@
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as generic guest with no PV drivers. Currently support
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||||
XEN HVM, KVM, HYPER_V and VMWARE guest.
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xen.balloon_boot_timeout= [XEN]
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The time (in seconds) to wait before giving up to boot
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in case initial ballooning fails to free enough memory.
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Applies only when running as HVM or PVH guest and
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started with less memory configured than allowed at
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max. Default is 180.
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xen.event_eoi_delay= [XEN]
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How long to delay EOI handling in case of event
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storms (jiffies). Default is 10.
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2
Makefile
2
Makefile
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@ -1,7 +1,7 @@
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|||
# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 4
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||||
SUBLEVEL = 147
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||||
SUBLEVEL = 161
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||||
EXTRAVERSION =
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NAME = Kleptomaniac Octopus
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|
||||
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|
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|||
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@ -1 +1 @@
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LTS_5.4.147_f2bbf1b7baa5
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LTS_5.4.161_b9d179c605d3
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|
|
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File diff suppressed because it is too large
Load diff
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@ -61,7 +61,7 @@ extern inline void set_hae(unsigned long new_hae)
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* Change virtual addresses to physical addresses and vv.
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*/
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#ifdef USE_48_BIT_KSEG
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static inline unsigned long virt_to_phys(void *address)
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static inline unsigned long virt_to_phys(volatile void *address)
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{
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return (unsigned long)address - IDENT_ADDR;
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}
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@ -71,7 +71,7 @@ static inline void * phys_to_virt(unsigned long address)
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return (void *) (address + IDENT_ADDR);
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}
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#else
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static inline unsigned long virt_to_phys(void *address)
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static inline unsigned long virt_to_phys(volatile void *address)
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{
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unsigned long phys = (unsigned long)address;
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@ -107,7 +107,7 @@ static inline void * phys_to_virt(unsigned long address)
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extern unsigned long __direct_map_base;
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extern unsigned long __direct_map_size;
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static inline unsigned long __deprecated virt_to_bus(void *address)
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static inline unsigned long __deprecated virt_to_bus(volatile void *address)
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{
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unsigned long phys = virt_to_phys(address);
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unsigned long bus = phys + __direct_map_base;
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|
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|
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@ -1123,7 +1123,7 @@ void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
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clear_page(to);
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clear_bit(PG_dc_clean, &page->flags);
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}
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|
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EXPORT_SYMBOL(clear_user_page);
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|
||||
/**********************************************************************
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||||
* Explicit Cache flush request from user space via syscall
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|
|
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|||
|
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@ -66,15 +66,15 @@ KBUILD_CFLAGS += $(call cc-option,-fno-ipa-sra)
|
|||
# Note that GCC does not numerically define an architecture version
|
||||
# macro, but instead defines a whole series of macros which makes
|
||||
# testing for a specific architecture or later rather impossible.
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arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
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arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
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arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
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arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m
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arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a
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arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6
|
||||
# Only override the compiler option if ARMv6. The ARMv6K extensions are
|
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# always available in ARMv7
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ifeq ($(CONFIG_CPU_32v6),y)
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arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
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arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 -march=armv6k
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endif
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arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
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arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 -march=armv5te
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arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t
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arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4
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arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m
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@ -88,7 +88,7 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM740T) =-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM9TDMI) =-mtune=arm9tdmi
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||||
tune-$(CONFIG_CPU_ARM940T) =-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM946E) =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
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tune-$(CONFIG_CPU_ARM946E) =-mtune=arm9e
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tune-$(CONFIG_CPU_ARM920T) =-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM922T) =-mtune=arm9tdmi
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||||
tune-$(CONFIG_CPU_ARM925T) =-mtune=arm9tdmi
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@ -96,11 +96,11 @@ tune-$(CONFIG_CPU_ARM926T) =-mtune=arm9tdmi
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tune-$(CONFIG_CPU_FA526) =-mtune=arm9tdmi
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tune-$(CONFIG_CPU_SA110) =-mtune=strongarm110
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||||
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
|
||||
tune-$(CONFIG_CPU_XSCALE) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
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||||
tune-$(CONFIG_CPU_XSC3) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
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||||
tune-$(CONFIG_CPU_FEROCEON) =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
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||||
tune-$(CONFIG_CPU_V6) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
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||||
tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
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||||
tune-$(CONFIG_CPU_XSCALE) =-mtune=xscale
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||||
tune-$(CONFIG_CPU_XSC3) =-mtune=xscale
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||||
tune-$(CONFIG_CPU_FEROCEON) =-mtune=xscale
|
||||
tune-$(CONFIG_CPU_V6) =-mtune=arm1136j-s
|
||||
tune-$(CONFIG_CPU_V6K) =-mtune=arm1136j-s
|
||||
|
||||
# Evaluate tune cc-option calls now
|
||||
tune-y := $(tune-y)
|
||||
|
|
|
|||
|
|
@ -90,6 +90,8 @@ $(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \
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|||
$(addprefix $(obj)/,$(libfdt_hdrs))
|
||||
|
||||
ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
|
||||
CFLAGS_REMOVE_atags_to_fdt.o += -Wframe-larger-than=${CONFIG_FRAME_WARN}
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||||
CFLAGS_atags_to_fdt.o += -Wframe-larger-than=1280
|
||||
OBJS += $(libfdt_objs) atags_to_fdt.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
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@ -47,7 +47,10 @@ extern char * strchrnul(const char *, int);
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_KERNEL_XZ
|
||||
/* Prevent KASAN override of string helpers in decompressor */
|
||||
#undef memmove
|
||||
#define memmove memmove
|
||||
#undef memcpy
|
||||
#define memcpy memcpy
|
||||
#include "../../../../lib/decompress_unxz.c"
|
||||
#endif
|
||||
|
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|
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|
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@ -69,7 +69,6 @@
|
|||
isc: isc@f0008000 {
|
||||
pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
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||||
status = "okay";
|
||||
};
|
||||
|
||||
qspi1: spi@f0024000 {
|
||||
|
|
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|||
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@ -262,7 +262,7 @@
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|||
&macb1 {
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status = "okay";
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||||
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rmii";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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||||
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|||
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@ -56,6 +56,7 @@
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|||
panel {
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||||
compatible = "edt,etm0700g0dh6";
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pinctrl-0 = <&pinctrl_display_gpio>;
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pinctrl-names = "default";
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||||
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
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||||
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port {
|
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|
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@ -76,8 +77,7 @@
|
|||
regulator-name = "vbus";
|
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regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
|
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gpio = <&gpio1 2 0>;
|
||||
};
|
||||
};
|
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|
||||
|
|
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@ -70,6 +70,12 @@
|
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clock-frequency = <11289600>;
|
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};
|
||||
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achc_24M: achc-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
|
||||
};
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|
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sgtlsound: sound {
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compatible = "fsl,imx53-cpuvo-sgtl5000",
|
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"fsl,imx-audio-sgtl5000";
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||||
|
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@ -287,16 +293,13 @@
|
|||
&gpio4 12 GPIO_ACTIVE_LOW>;
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status = "okay";
|
||||
|
||||
spidev0: spi@0 {
|
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compatible = "ge,achc";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
|
||||
spidev1: spi@1 {
|
||||
compatible = "ge,achc";
|
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reg = <1>;
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spi-max-frequency = <1000000>;
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||||
spidev0: spi@1 {
|
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compatible = "ge,achc", "nxp,kinetis-k20";
|
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reg = <1>, <0>;
|
||||
vdd-supply = <®_3v3>;
|
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vdda-supply = <®_3v3>;
|
||||
clocks = <&achc_24M>;
|
||||
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
gpioxra0: gpio@2 {
|
||||
|
|
|
|||
|
|
@ -515,7 +515,7 @@
|
|||
compatible = "bosch,bma180";
|
||||
reg = <0x41>;
|
||||
pinctrl-names = "default";
|
||||
pintcrl-0 = <&bma180_pins>;
|
||||
pinctrl-0 = <&bma180_pins>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@
|
|||
|
||||
nand@1,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@
|
|||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
pxo_board {
|
||||
pxo_board: pxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
|
|
@ -1147,7 +1147,7 @@
|
|||
};
|
||||
|
||||
gpu: adreno-3xx@4300000 {
|
||||
compatible = "qcom,adreno-3xx";
|
||||
compatible = "qcom,adreno-320.2", "qcom,adreno";
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -1162,7 +1162,6 @@
|
|||
<&mmcc GFX3D_AHB_CLK>,
|
||||
<&mmcc GFX3D_AXI_CLK>,
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
qcom,chipid = <0x03020002>;
|
||||
|
||||
iommus = <&gfx3d 0
|
||||
&gfx3d 1
|
||||
|
|
@ -1261,9 +1260,9 @@
|
|||
<&mmcc DSI1_BYTE_CLK>,
|
||||
<&mmcc DSI_PIXEL_CLK>,
|
||||
<&mmcc DSI1_ESC_CLK>;
|
||||
clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
|
||||
"src_clk", "byte_clk", "pixel_clk",
|
||||
"core_clk";
|
||||
clock-names = "iface", "bus", "core_mmss",
|
||||
"src", "byte", "pixel",
|
||||
"core";
|
||||
|
||||
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
|
||||
<&mmcc DSI1_ESC_SRC>,
|
||||
|
|
@ -1305,7 +1304,7 @@
|
|||
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
|
||||
clock-names = "iface_clk", "ref";
|
||||
clocks = <&mmcc DSI_M_AHB_CLK>,
|
||||
<&cxo_board>;
|
||||
<&pxo_board>;
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1213,8 +1213,8 @@
|
|||
#phy-cells = <0>;
|
||||
qcom,dsi-phy-index = <0>;
|
||||
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
clock-names = "iface";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
};
|
||||
|
||||
gmac: eth@e0800000 {
|
||||
compatible = "st,spear600-gmac";
|
||||
compatible = "snps,dwmac-3.40a";
|
||||
reg = <0xe0800000 0x8000>;
|
||||
interrupts = <23 22>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
|
|
|
|||
|
|
@ -773,7 +773,7 @@
|
|||
#sound-dai-cells = <0>;
|
||||
|
||||
compatible = "st,stm32-sai-sub-a";
|
||||
reg = <0x4 0x1c>;
|
||||
reg = <0x4 0x20>;
|
||||
clocks = <&rcc SAI1_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 87 0x400 0x01>;
|
||||
|
|
@ -783,7 +783,7 @@
|
|||
sai1b: audio-controller@4400a024 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-b";
|
||||
reg = <0x24 0x1c>;
|
||||
reg = <0x24 0x20>;
|
||||
clocks = <&rcc SAI1_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 88 0x400 0x01>;
|
||||
|
|
@ -804,7 +804,7 @@
|
|||
sai2a: audio-controller@4400b004 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-a";
|
||||
reg = <0x4 0x1c>;
|
||||
reg = <0x4 0x20>;
|
||||
clocks = <&rcc SAI2_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 89 0x400 0x01>;
|
||||
|
|
@ -814,7 +814,7 @@
|
|||
sai2b: audio-controller@4400b024 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-b";
|
||||
reg = <0x24 0x1c>;
|
||||
reg = <0x24 0x20>;
|
||||
clocks = <&rcc SAI2_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 90 0x400 0x01>;
|
||||
|
|
@ -835,7 +835,7 @@
|
|||
sai3a: audio-controller@4400c004 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-a";
|
||||
reg = <0x04 0x1c>;
|
||||
reg = <0x04 0x20>;
|
||||
clocks = <&rcc SAI3_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 113 0x400 0x01>;
|
||||
|
|
@ -845,7 +845,7 @@
|
|||
sai3b: audio-controller@4400c024 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-b";
|
||||
reg = <0x24 0x1c>;
|
||||
reg = <0x24 0x20>;
|
||||
clocks = <&rcc SAI3_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 114 0x400 0x01>;
|
||||
|
|
@ -1191,7 +1191,7 @@
|
|||
sai4a: audio-controller@50027004 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-a";
|
||||
reg = <0x04 0x1c>;
|
||||
reg = <0x04 0x20>;
|
||||
clocks = <&rcc SAI4_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 99 0x400 0x01>;
|
||||
|
|
@ -1201,7 +1201,7 @@
|
|||
sai4b: audio-controller@50027024 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "st,stm32-sai-sub-b";
|
||||
reg = <0x24 0x1c>;
|
||||
reg = <0x24 0x20>;
|
||||
clocks = <&rcc SAI4_K>;
|
||||
clock-names = "sai_ck";
|
||||
dmas = <&dmamux1 100 0x400 0x01>;
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -185,8 +185,9 @@
|
|||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "cdev2", "dap1", "dtb", "gma",
|
||||
"gmb", "gmc", "gmd", "gme", "gpu7",
|
||||
"gpv", "i2cp", "pta", "rm", "slxa",
|
||||
"slxk", "spia", "spib", "uac";
|
||||
"gpv", "i2cp", "irrx", "irtx", "pta",
|
||||
"rm", "slxa", "slxk", "spia", "spib",
|
||||
"uac";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
|
@ -211,7 +212,7 @@
|
|||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"sdc";
|
||||
"sdc", "uad", "uca";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
|
@ -221,10 +222,9 @@
|
|||
"lvp0", "owc", "sdb";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
||||
"spie", "spih", "uaa", "uab", "uad",
|
||||
"uca", "ucb";
|
||||
conf_sdd {
|
||||
nvidia,pins = "sdd", "spic", "spie", "spih",
|
||||
"uaa", "uab", "ucb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,9 @@ extern void __gnu_mcount_nc(void);
|
|||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
struct dyn_arch_ftrace {
|
||||
#ifdef CONFIG_ARM_MODULE_PLTS
|
||||
struct module *mod;
|
||||
#endif
|
||||
};
|
||||
|
||||
static inline unsigned long ftrace_call_adjust(unsigned long addr)
|
||||
|
|
|
|||
|
|
@ -13,18 +13,18 @@ arm_gen_nop(void)
|
|||
}
|
||||
|
||||
unsigned long
|
||||
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link);
|
||||
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link, bool warn);
|
||||
|
||||
static inline unsigned long
|
||||
arm_gen_branch(unsigned long pc, unsigned long addr)
|
||||
{
|
||||
return __arm_gen_branch(pc, addr, false);
|
||||
return __arm_gen_branch(pc, addr, false, true);
|
||||
}
|
||||
|
||||
static inline unsigned long
|
||||
arm_gen_branch_link(unsigned long pc, unsigned long addr)
|
||||
arm_gen_branch_link(unsigned long pc, unsigned long addr, bool warn)
|
||||
{
|
||||
return __arm_gen_branch(pc, addr, true);
|
||||
return __arm_gen_branch(pc, addr, true, warn);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -19,8 +19,18 @@ enum {
|
|||
};
|
||||
#endif
|
||||
|
||||
#define PLT_ENT_STRIDE L1_CACHE_BYTES
|
||||
#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32))
|
||||
#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT)
|
||||
|
||||
struct plt_entries {
|
||||
u32 ldr[PLT_ENT_COUNT];
|
||||
u32 lit[PLT_ENT_COUNT];
|
||||
};
|
||||
|
||||
struct mod_plt_sec {
|
||||
struct elf32_shdr *plt;
|
||||
struct plt_entries *plt_ent;
|
||||
int plt_count;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -71,9 +71,10 @@ int ftrace_arch_code_modify_post_process(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
|
||||
static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr,
|
||||
bool warn)
|
||||
{
|
||||
return arm_gen_branch_link(pc, addr);
|
||||
return arm_gen_branch_link(pc, addr, warn);
|
||||
}
|
||||
|
||||
static int ftrace_modify_code(unsigned long pc, unsigned long old,
|
||||
|
|
@ -112,14 +113,14 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
|
|||
int ret;
|
||||
|
||||
pc = (unsigned long)&ftrace_call;
|
||||
new = ftrace_call_replace(pc, (unsigned long)func);
|
||||
new = ftrace_call_replace(pc, (unsigned long)func, true);
|
||||
|
||||
ret = ftrace_modify_code(pc, 0, new, false);
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS
|
||||
if (!ret) {
|
||||
pc = (unsigned long)&ftrace_regs_call;
|
||||
new = ftrace_call_replace(pc, (unsigned long)func);
|
||||
new = ftrace_call_replace(pc, (unsigned long)func, true);
|
||||
|
||||
ret = ftrace_modify_code(pc, 0, new, false);
|
||||
}
|
||||
|
|
@ -132,10 +133,22 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
|
|||
{
|
||||
unsigned long new, old;
|
||||
unsigned long ip = rec->ip;
|
||||
unsigned long aaddr = adjust_address(rec, addr);
|
||||
struct module *mod = NULL;
|
||||
|
||||
#ifdef CONFIG_ARM_MODULE_PLTS
|
||||
mod = rec->arch.mod;
|
||||
#endif
|
||||
|
||||
old = ftrace_nop_replace(rec);
|
||||
|
||||
new = ftrace_call_replace(ip, adjust_address(rec, addr));
|
||||
new = ftrace_call_replace(ip, aaddr, !mod);
|
||||
#ifdef CONFIG_ARM_MODULE_PLTS
|
||||
if (!new && mod) {
|
||||
aaddr = get_module_plt(mod, ip, aaddr);
|
||||
new = ftrace_call_replace(ip, aaddr, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ftrace_modify_code(rec->ip, old, new, true);
|
||||
}
|
||||
|
|
@ -148,9 +161,9 @@ int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
|
|||
unsigned long new, old;
|
||||
unsigned long ip = rec->ip;
|
||||
|
||||
old = ftrace_call_replace(ip, adjust_address(rec, old_addr));
|
||||
old = ftrace_call_replace(ip, adjust_address(rec, old_addr), true);
|
||||
|
||||
new = ftrace_call_replace(ip, adjust_address(rec, addr));
|
||||
new = ftrace_call_replace(ip, adjust_address(rec, addr), true);
|
||||
|
||||
return ftrace_modify_code(rec->ip, old, new, true);
|
||||
}
|
||||
|
|
@ -160,12 +173,29 @@ int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
|
|||
int ftrace_make_nop(struct module *mod,
|
||||
struct dyn_ftrace *rec, unsigned long addr)
|
||||
{
|
||||
unsigned long aaddr = adjust_address(rec, addr);
|
||||
unsigned long ip = rec->ip;
|
||||
unsigned long old;
|
||||
unsigned long new;
|
||||
int ret;
|
||||
|
||||
old = ftrace_call_replace(ip, adjust_address(rec, addr));
|
||||
#ifdef CONFIG_ARM_MODULE_PLTS
|
||||
/* mod is only supplied during module loading */
|
||||
if (!mod)
|
||||
mod = rec->arch.mod;
|
||||
else
|
||||
rec->arch.mod = mod;
|
||||
#endif
|
||||
|
||||
old = ftrace_call_replace(ip, aaddr,
|
||||
!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || !mod);
|
||||
#ifdef CONFIG_ARM_MODULE_PLTS
|
||||
if (!old && mod) {
|
||||
aaddr = get_module_plt(mod, ip, aaddr);
|
||||
old = ftrace_call_replace(ip, aaddr, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
new = ftrace_nop_replace(rec);
|
||||
ret = ftrace_modify_code(ip, old, new, true);
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,9 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <asm/opcodes.h>
|
||||
|
||||
static unsigned long
|
||||
__arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
|
||||
static unsigned long __arm_gen_branch_thumb2(unsigned long pc,
|
||||
unsigned long addr, bool link,
|
||||
bool warn)
|
||||
{
|
||||
unsigned long s, j1, j2, i1, i2, imm10, imm11;
|
||||
unsigned long first, second;
|
||||
|
|
@ -12,7 +13,7 @@ __arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
|
|||
|
||||
offset = (long)addr - (long)(pc + 4);
|
||||
if (offset < -16777216 || offset > 16777214) {
|
||||
WARN_ON_ONCE(1);
|
||||
WARN_ON_ONCE(warn);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -33,8 +34,8 @@ __arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
|
|||
return __opcode_thumb32_compose(first, second);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
__arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
|
||||
static unsigned long __arm_gen_branch_arm(unsigned long pc, unsigned long addr,
|
||||
bool link, bool warn)
|
||||
{
|
||||
unsigned long opcode = 0xea000000;
|
||||
long offset;
|
||||
|
|
@ -44,7 +45,7 @@ __arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
|
|||
|
||||
offset = (long)addr - (long)(pc + 8);
|
||||
if (unlikely(offset < -33554432 || offset > 33554428)) {
|
||||
WARN_ON_ONCE(1);
|
||||
WARN_ON_ONCE(warn);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -54,10 +55,10 @@ __arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
|
|||
}
|
||||
|
||||
unsigned long
|
||||
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link)
|
||||
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link, bool warn)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_THUMB2_KERNEL))
|
||||
return __arm_gen_branch_thumb2(pc, addr, link);
|
||||
return __arm_gen_branch_thumb2(pc, addr, link, warn);
|
||||
else
|
||||
return __arm_gen_branch_arm(pc, addr, link);
|
||||
return __arm_gen_branch_arm(pc, addr, link, warn);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/elf.h>
|
||||
#include <linux/ftrace.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sort.h>
|
||||
|
|
@ -11,10 +12,6 @@
|
|||
#include <asm/cache.h>
|
||||
#include <asm/opcodes.h>
|
||||
|
||||
#define PLT_ENT_STRIDE L1_CACHE_BYTES
|
||||
#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32))
|
||||
#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT)
|
||||
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
#define PLT_ENT_LDR __opcode_to_mem_thumb32(0xf8dff000 | \
|
||||
(PLT_ENT_STRIDE - 4))
|
||||
|
|
@ -23,9 +20,11 @@
|
|||
(PLT_ENT_STRIDE - 8))
|
||||
#endif
|
||||
|
||||
struct plt_entries {
|
||||
u32 ldr[PLT_ENT_COUNT];
|
||||
u32 lit[PLT_ENT_COUNT];
|
||||
static const u32 fixed_plts[] = {
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
FTRACE_ADDR,
|
||||
MCOUNT_ADDR,
|
||||
#endif
|
||||
};
|
||||
|
||||
static bool in_init(const struct module *mod, unsigned long loc)
|
||||
|
|
@ -33,14 +32,40 @@ static bool in_init(const struct module *mod, unsigned long loc)
|
|||
return loc - (u32)mod->init_layout.base < mod->init_layout.size;
|
||||
}
|
||||
|
||||
static void prealloc_fixed(struct mod_plt_sec *pltsec, struct plt_entries *plt)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!ARRAY_SIZE(fixed_plts) || pltsec->plt_count)
|
||||
return;
|
||||
pltsec->plt_count = ARRAY_SIZE(fixed_plts);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(plt->ldr); ++i)
|
||||
plt->ldr[i] = PLT_ENT_LDR;
|
||||
|
||||
BUILD_BUG_ON(sizeof(fixed_plts) > sizeof(plt->lit));
|
||||
memcpy(plt->lit, fixed_plts, sizeof(fixed_plts));
|
||||
}
|
||||
|
||||
u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val)
|
||||
{
|
||||
struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
|
||||
&mod->arch.init;
|
||||
struct plt_entries *plt;
|
||||
int idx;
|
||||
|
||||
struct plt_entries *plt = (struct plt_entries *)pltsec->plt->sh_addr;
|
||||
int idx = 0;
|
||||
/* cache the address, ELF header is available only during module load */
|
||||
if (!pltsec->plt_ent)
|
||||
pltsec->plt_ent = (struct plt_entries *)pltsec->plt->sh_addr;
|
||||
plt = pltsec->plt_ent;
|
||||
|
||||
prealloc_fixed(pltsec, plt);
|
||||
|
||||
for (idx = 0; idx < ARRAY_SIZE(fixed_plts); ++idx)
|
||||
if (plt->lit[idx] == val)
|
||||
return (u32)&plt->ldr[idx];
|
||||
|
||||
idx = 0;
|
||||
/*
|
||||
* Look for an existing entry pointing to 'val'. Given that the
|
||||
* relocations are sorted, this will be the last entry we allocated.
|
||||
|
|
@ -188,8 +213,8 @@ static unsigned int count_plts(const Elf32_Sym *syms, Elf32_Addr base,
|
|||
int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
|
||||
char *secstrings, struct module *mod)
|
||||
{
|
||||
unsigned long core_plts = 0;
|
||||
unsigned long init_plts = 0;
|
||||
unsigned long core_plts = ARRAY_SIZE(fixed_plts);
|
||||
unsigned long init_plts = ARRAY_SIZE(fixed_plts);
|
||||
Elf32_Shdr *s, *sechdrs_end = sechdrs + ehdr->e_shnum;
|
||||
Elf32_Sym *syms = NULL;
|
||||
|
||||
|
|
@ -244,6 +269,7 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
|
|||
mod->arch.core.plt->sh_size = round_up(core_plts * PLT_ENT_SIZE,
|
||||
sizeof(struct plt_entries));
|
||||
mod->arch.core.plt_count = 0;
|
||||
mod->arch.core.plt_ent = NULL;
|
||||
|
||||
mod->arch.init.plt->sh_type = SHT_NOBITS;
|
||||
mod->arch.init.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
|
||||
|
|
@ -251,6 +277,7 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
|
|||
mod->arch.init.plt->sh_size = round_up(init_plts * PLT_ENT_SIZE,
|
||||
sizeof(struct plt_entries));
|
||||
mod->arch.init.plt_count = 0;
|
||||
mod->arch.init.plt_ent = NULL;
|
||||
|
||||
pr_debug("%s: plt=%x, init.plt=%x\n", __func__,
|
||||
mod->arch.core.plt->sh_size, mod->arch.init.plt->sh_size);
|
||||
|
|
|
|||
|
|
@ -54,8 +54,7 @@ int notrace unwind_frame(struct stackframe *frame)
|
|||
|
||||
frame->sp = frame->fp;
|
||||
frame->fp = *(unsigned long *)(fp);
|
||||
frame->pc = frame->lr;
|
||||
frame->lr = *(unsigned long *)(fp + 4);
|
||||
frame->pc = *(unsigned long *)(fp + 4);
|
||||
#else
|
||||
/* check current frame pointer is within bounds */
|
||||
if (fp < low + 12 || fp > high - 4)
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@ ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & PAGE_MASK) <= PAGE_SIZE,
|
|||
ASSERT((_end - __bss_start) >= 12288, ".bss too small for CONFIG_XIP_DEFLATED_DATA")
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
#if defined(CONFIG_ARM_MPU) && !defined(CONFIG_COMPILE_TEST)
|
||||
/*
|
||||
* Due to PMSAv7 restriction on base address and size we have to
|
||||
* enforce minimal alignment restrictions. It was seen that weaker
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
|
||||
#include <linux/of.h>
|
||||
|
|
@ -618,6 +619,7 @@ static void __init imx6_pm_common_init(const struct imx6_pm_socdata
|
|||
|
||||
static void imx6_pm_stby_poweroff(void)
|
||||
{
|
||||
gic_cpu_if_down(0);
|
||||
imx6_set_lpm(STOP_POWER_OFF);
|
||||
imx6q_suspend_finish(0);
|
||||
|
||||
|
|
|
|||
|
|
@ -3656,6 +3656,8 @@ int omap_hwmod_init_module(struct device *dev,
|
|||
oh->flags |= HWMOD_SWSUP_SIDLE_ACT;
|
||||
if (data->cfg->quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
|
||||
oh->flags |= HWMOD_SWSUP_MSTANDBY;
|
||||
if (data->cfg->quirks & SYSC_QUIRK_CLKDM_NOAUTO)
|
||||
oh->flags |= HWMOD_CLKDM_NOAUTO;
|
||||
|
||||
error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
|
||||
rev_offs, sysc_offs, syss_offs,
|
||||
|
|
|
|||
|
|
@ -752,7 +752,7 @@ config CPU_BIG_ENDIAN
|
|||
config CPU_ENDIAN_BE8
|
||||
bool
|
||||
depends on CPU_BIG_ENDIAN
|
||||
default CPU_V6 || CPU_V6K || CPU_V7
|
||||
default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
|
||||
help
|
||||
Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
|
||||
|
||||
|
|
|
|||
|
|
@ -519,7 +519,11 @@ static void print_vmalloc_lowmem_info(void)
|
|||
void __init mem_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ARM_LPAE
|
||||
swiotlb_init(1);
|
||||
if (swiotlb_force == SWIOTLB_FORCE ||
|
||||
max_pfn > arm_dma_pfn_limit)
|
||||
swiotlb_init(1);
|
||||
else
|
||||
swiotlb_force = SWIOTLB_NO_FORCE;
|
||||
#endif
|
||||
|
||||
set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
|
||||
|
|
|
|||
|
|
@ -415,9 +415,9 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
|
|||
FIXADDR_END);
|
||||
BUG_ON(idx >= __end_of_fixed_addresses);
|
||||
|
||||
/* we only support device mappings until pgprot_kernel has been set */
|
||||
/* We support only device mappings before pgprot_kernel is set. */
|
||||
if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
|
||||
pgprot_val(pgprot_kernel) == 0))
|
||||
pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
|
||||
return;
|
||||
|
||||
if (pgprot_val(prot))
|
||||
|
|
|
|||
|
|
@ -342,6 +342,7 @@ ENTRY(\name\()_cache_fns)
|
|||
|
||||
.macro define_tlb_functions name:req, flags_up:req, flags_smp
|
||||
.type \name\()_tlb_fns, #object
|
||||
.align 2
|
||||
ENTRY(\name\()_tlb_fns)
|
||||
.long \name\()_flush_user_tlb_range
|
||||
.long \name\()_flush_kern_tlb_range
|
||||
|
|
|
|||
|
|
@ -36,6 +36,10 @@
|
|||
* +-----+
|
||||
* |RSVD | JIT scratchpad
|
||||
* current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
|
||||
* | ... | caller-saved registers
|
||||
* +-----+
|
||||
* | ... | arguments passed on stack
|
||||
* ARM_SP during call => +-----|
|
||||
* | |
|
||||
* | ... | Function call stack
|
||||
* | |
|
||||
|
|
@ -63,6 +67,12 @@
|
|||
*
|
||||
* When popping registers off the stack at the end of a BPF function, we
|
||||
* reference them via the current ARM_FP register.
|
||||
*
|
||||
* Some eBPF operations are implemented via a call to a helper function.
|
||||
* Such calls are "invisible" in the eBPF code, so it is up to the calling
|
||||
* program to preserve any caller-saved ARM registers during the call. The
|
||||
* JIT emits code to push and pop those registers onto the stack, immediately
|
||||
* above the callee stack frame.
|
||||
*/
|
||||
#define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
|
||||
1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
|
||||
|
|
@ -70,6 +80,8 @@
|
|||
#define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
|
||||
#define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
|
||||
|
||||
#define CALLER_MASK (1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3)
|
||||
|
||||
enum {
|
||||
/* Stack layout - these are offsets from (top of stack - 4) */
|
||||
BPF_R2_HI,
|
||||
|
|
@ -464,6 +476,7 @@ static inline int epilogue_offset(const struct jit_ctx *ctx)
|
|||
|
||||
static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
|
||||
{
|
||||
const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1);
|
||||
const s8 *tmp = bpf2a32[TMP_REG_1];
|
||||
|
||||
#if __LINUX_ARM_ARCH__ == 7
|
||||
|
|
@ -495,11 +508,17 @@ static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
|
|||
emit(ARM_MOV_R(ARM_R0, rm), ctx);
|
||||
}
|
||||
|
||||
/* Push caller-saved registers on stack */
|
||||
emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx);
|
||||
|
||||
/* Call appropriate function */
|
||||
emit_mov_i(ARM_IP, op == BPF_DIV ?
|
||||
(u32)jit_udiv32 : (u32)jit_mod32, ctx);
|
||||
emit_blx_r(ARM_IP, ctx);
|
||||
|
||||
/* Restore caller-saved registers from stack */
|
||||
emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx);
|
||||
|
||||
/* Save return value */
|
||||
if (rd != ARM_R0)
|
||||
emit(ARM_MOV_R(rd, ARM_R0), ctx);
|
||||
|
|
|
|||
|
|
@ -534,7 +534,7 @@ static struct undef_hook kprobes_arm_break_hook = {
|
|||
|
||||
#endif /* !CONFIG_THUMB2_KERNEL */
|
||||
|
||||
int __init arch_init_kprobes()
|
||||
int __init arch_init_kprobes(void)
|
||||
{
|
||||
arm_probes_decode_init();
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@
|
|||
pinctrl-0 = <&emac_rgmii_pins>;
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@
|
|||
regulator-min-microvolt = <721000>;
|
||||
regulator-max-microvolt = <1022000>;
|
||||
|
||||
vin-supply = <&dc_in>;
|
||||
pwm-supply = <&dc_in>;
|
||||
|
||||
pwms = <&pwm_AO_cd 1 1250 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@
|
|||
regulator-min-microvolt = <721000>;
|
||||
regulator-max-microvolt = <1022000>;
|
||||
|
||||
vin-supply = <&main_12v>;
|
||||
pwm-supply = <&main_12v>;
|
||||
|
||||
pwms = <&pwm_AO_cd 1 1250 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@
|
|||
regulator-min-microvolt = <721000>;
|
||||
regulator-max-microvolt = <1022000>;
|
||||
|
||||
vin-supply = <&dc_in>;
|
||||
pwm-supply = <&dc_in>;
|
||||
|
||||
pwms = <&pwm_AO_cd 1 1250 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
|
|
|||
|
|
@ -287,6 +287,24 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
can0: can@2180000 {
|
||||
compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysclk>, <&clockgen 4 1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@2190000 {
|
||||
compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysclk>, <&clockgen 4 1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
|
|
@ -496,14 +514,14 @@
|
|||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0 0xc000000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster1_core1_watchdog: watchdog@c010000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0 0xc010000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
sai1: audio-controller@f100000 {
|
||||
|
|
|
|||
|
|
@ -83,15 +83,9 @@
|
|||
};
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c512";
|
||||
compatible = "onnn,cat24c04", "atmel,24c04";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -58,14 +58,9 @@
|
|||
};
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c512";
|
||||
compatible = "onnn,cat24c05", "atmel,24c04";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
|
|
|
|||
|
|
@ -640,56 +640,56 @@
|
|||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc000000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster1_core1_watchdog: wdt@c010000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc010000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster1_core2_watchdog: wdt@c020000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc020000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster1_core3_watchdog: wdt@c030000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc030000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster2_core0_watchdog: wdt@c100000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc100000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster2_core1_watchdog: wdt@c110000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc110000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster2_core2_watchdog: wdt@c120000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc120000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster2_core3_watchdog: wdt@c130000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc130000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
fsl_mc: fsl-mc@80c000000 {
|
||||
|
|
|
|||
|
|
@ -230,56 +230,56 @@
|
|||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc000000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster1_core1_watchdog: wdt@c010000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc010000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster2_core0_watchdog: wdt@c100000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc100000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster2_core1_watchdog: wdt@c110000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc110000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster3_core0_watchdog: wdt@c200000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc200000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster3_core1_watchdog: wdt@c210000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc210000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster4_core0_watchdog: wdt@c300000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc300000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
cluster4_core1_watchdog: wdt@c310000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
reg = <0x0 0xc310000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "apb_pclk", "wdog_clk";
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
crypto: crypto@8000000 {
|
||||
|
|
|
|||
|
|
@ -138,6 +138,23 @@
|
|||
max-link-speed = <2>;
|
||||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
phys = <&comphy1 0>;
|
||||
/*
|
||||
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
|
||||
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
|
||||
* 2 size cells and also expects that the second range starts at 16 MB offset. If these
|
||||
* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
|
||||
* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
|
||||
* for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
|
||||
* This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
|
||||
* U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
|
||||
*/
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
|
||||
0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
|
||||
|
||||
/* enabled by U-Boot if PCIe module is present */
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -487,8 +487,15 @@
|
|||
#interrupt-cells = <1>;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-controller;
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
|
||||
0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
|
||||
/*
|
||||
* The 128 MiB address range [0xe8000000-0xf0000000] is
|
||||
* dedicated for PCIe and can be assigned to 8 windows
|
||||
* with size a power of two. Use one 64 KiB window for
|
||||
* IO at the end and the remaining seven windows
|
||||
* (totaling 127 MiB) for MEM.
|
||||
*/
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
|
||||
0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
|
|
|
|||
|
|
@ -1082,13 +1082,13 @@
|
|||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "nvidia,denver";
|
||||
compatible = "nvidia,tegra132-denver";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "nvidia,denver";
|
||||
compatible = "nvidia,tegra132-denver";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1434,7 +1434,7 @@
|
|||
};
|
||||
|
||||
pcie_ep@14160000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
compatible = "nvidia,tegra194-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
||||
reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
|
|
@ -1466,7 +1466,7 @@
|
|||
};
|
||||
|
||||
pcie_ep@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
compatible = "nvidia,tegra194-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
|
|
@ -1498,7 +1498,7 @@
|
|||
};
|
||||
|
||||
pcie_ep@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
compatible = "nvidia,tegra194-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0x0 0x20000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
pon: power-on@800 {
|
||||
compatible = "qcom,pm8916-pon";
|
||||
compatible = "qcom,pm8998-pon";
|
||||
reg = <0x0800>;
|
||||
pwrkey {
|
||||
compatible = "qcom,pm8941-pwrkey";
|
||||
|
|
|
|||
|
|
@ -555,7 +555,7 @@
|
|||
|
||||
gpu: gpu@ff300000 {
|
||||
compatible = "rockchip,rk3328-mali", "arm,mali-450";
|
||||
reg = <0x0 0xff300000 0x0 0x40000>;
|
||||
reg = <0x0 0xff300000 0x0 0x30000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
|
|||
|
|
@ -552,7 +552,6 @@ CONFIG_SECURITYFS=y
|
|||
CONFIG_SECURITY_NETWORK=y
|
||||
CONFIG_HARDENED_USERCOPY=y
|
||||
# CONFIG_HARDENED_USERCOPY_FALLBACK is not set
|
||||
CONFIG_FORTIFY_SOURCE=y
|
||||
CONFIG_STATIC_USERMODEHELPER=y
|
||||
CONFIG_STATIC_USERMODEHELPER_PATH=""
|
||||
CONFIG_SECURITY_SELINUX=y
|
||||
|
|
|
|||
|
|
@ -264,7 +264,6 @@ CONFIG_SECURITY=y
|
|||
CONFIG_SECURITY_NETWORK=y
|
||||
CONFIG_HARDENED_USERCOPY=y
|
||||
# CONFIG_HARDENED_USERCOPY_FALLBACK is not set
|
||||
CONFIG_FORTIFY_SOURCE=y
|
||||
CONFIG_SECURITY_SELINUX=y
|
||||
CONFIG_LSM="selinux"
|
||||
CONFIG_CRYPTO_AUTHENC=m
|
||||
|
|
|
|||
|
|
@ -65,8 +65,8 @@
|
|||
#define EARLY_KASLR (0)
|
||||
#endif
|
||||
|
||||
#define EARLY_ENTRIES(vstart, vend, shift) (((vend) >> (shift)) \
|
||||
- ((vstart) >> (shift)) + 1 + EARLY_KASLR)
|
||||
#define EARLY_ENTRIES(vstart, vend, shift) \
|
||||
((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1 + EARLY_KASLR)
|
||||
|
||||
#define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT))
|
||||
|
||||
|
|
|
|||
|
|
@ -54,9 +54,15 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
|
|||
* page table entry, taking care of 52-bit addresses.
|
||||
*/
|
||||
#ifdef CONFIG_ARM64_PA_BITS_52
|
||||
#define __pte_to_phys(pte) \
|
||||
((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
|
||||
#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
|
||||
static inline phys_addr_t __pte_to_phys(pte_t pte)
|
||||
{
|
||||
return (pte_val(pte) & PTE_ADDR_LOW) |
|
||||
((pte_val(pte) & PTE_ADDR_HIGH) << 36);
|
||||
}
|
||||
static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
|
||||
{
|
||||
return (phys | (phys >> 36)) & PTE_ADDR_MASK;
|
||||
}
|
||||
#else
|
||||
#define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
|
||||
#define __phys_to_pte_val(phys) (phys)
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
|
|||
this_leaf->type = type;
|
||||
}
|
||||
|
||||
static int __init_cache_level(unsigned int cpu)
|
||||
int init_cache_level(unsigned int cpu)
|
||||
{
|
||||
unsigned int ctype, level, leaves, fw_level;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
|
@ -78,7 +78,7 @@ static int __init_cache_level(unsigned int cpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int __populate_cache_leaves(unsigned int cpu)
|
||||
int populate_cache_leaves(unsigned int cpu)
|
||||
{
|
||||
unsigned int level, idx;
|
||||
enum cache_type type;
|
||||
|
|
@ -97,6 +97,3 @@ static int __populate_cache_leaves(unsigned int cpu)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
|
||||
DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
|
||||
|
|
|
|||
|
|
@ -498,7 +498,7 @@ size_t sve_state_size(struct task_struct const *task)
|
|||
void sve_alloc(struct task_struct *task)
|
||||
{
|
||||
if (task->thread.sve_state) {
|
||||
memset(task->thread.sve_state, 0, sve_state_size(current));
|
||||
memset(task->thread.sve_state, 0, sve_state_size(task));
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ ENDPROC(preserve_boot_args)
|
|||
* to be composed of multiple pages. (This effectively scales the end index).
|
||||
*
|
||||
* vstart: virtual address of start of range
|
||||
* vend: virtual address of end of range
|
||||
* vend: virtual address of end of range - we map [vstart, vend]
|
||||
* shift: shift used to transform virtual address into index
|
||||
* ptrs: number of entries in page table
|
||||
* istart: index in table corresponding to vstart
|
||||
|
|
@ -232,17 +232,18 @@ ENDPROC(preserve_boot_args)
|
|||
*
|
||||
* tbl: location of page table
|
||||
* rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
|
||||
* vstart: start address to map
|
||||
* vend: end address to map - we map [vstart, vend]
|
||||
* vstart: virtual address of start of range
|
||||
* vend: virtual address of end of range - we map [vstart, vend - 1]
|
||||
* flags: flags to use to map last level entries
|
||||
* phys: physical address corresponding to vstart - physical memory is contiguous
|
||||
* pgds: the number of pgd entries
|
||||
*
|
||||
* Temporaries: istart, iend, tmp, count, sv - these need to be different registers
|
||||
* Preserves: vstart, vend, flags
|
||||
* Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
|
||||
* Preserves: vstart, flags
|
||||
* Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv
|
||||
*/
|
||||
.macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
|
||||
sub \vend, \vend, #1
|
||||
add \rtbl, \tbl, #PAGE_SIZE
|
||||
mov \sv, \rtbl
|
||||
mov \count, #0
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
|
||||
#include <linux/stackprotector.h>
|
||||
unsigned long __stack_chk_guard __read_mostly;
|
||||
unsigned long __stack_chk_guard __ro_after_init;
|
||||
EXPORT_SYMBOL(__stack_chk_guard);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -996,6 +996,11 @@ out:
|
|||
return prog;
|
||||
}
|
||||
|
||||
u64 bpf_jit_alloc_exec_limit(void)
|
||||
{
|
||||
return BPF_JIT_REGION_SIZE;
|
||||
}
|
||||
|
||||
void *bpf_jit_alloc_exec(unsigned long size)
|
||||
{
|
||||
return __vmalloc_node_range(size, PAGE_SIZE, BPF_JIT_REGION_START,
|
||||
|
|
|
|||
|
|
@ -96,7 +96,8 @@ static int gpr_set(struct task_struct *target,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
regs.sr = task_pt_regs(target)->sr;
|
||||
/* BIT(0) of regs.sr is Condition Code/Carry bit */
|
||||
regs.sr = (regs.sr & BIT(0)) | (task_pt_regs(target)->sr & ~BIT(0));
|
||||
#ifdef CONFIG_CPU_HAS_HILO
|
||||
regs.dcsr = task_pt_regs(target)->dcsr;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -52,10 +52,14 @@ static long restore_sigcontext(struct pt_regs *regs,
|
|||
struct sigcontext __user *sc)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned long sr = regs->sr;
|
||||
|
||||
/* sc_pt_regs is structured the same as the start of pt_regs */
|
||||
err |= __copy_from_user(regs, &sc->sc_pt_regs, sizeof(struct pt_regs));
|
||||
|
||||
/* BIT(0) of regs->sr is Condition Code/Carry bit */
|
||||
regs->sr = (sr & ~1) | (regs->sr & 1);
|
||||
|
||||
/* Restore the floating-point state. */
|
||||
err |= restore_fpu_state(sc);
|
||||
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ config DISABLE_VHPT
|
|||
|
||||
config IA64_DEBUG_CMPXCHG
|
||||
bool "Turn on compare-and-exchange bug checking (slow!)"
|
||||
depends on DEBUG_KERNEL
|
||||
depends on DEBUG_KERNEL && PRINTK
|
||||
help
|
||||
Selecting this option turns on bug checking for the IA-64
|
||||
compare-and-exchange instructions. This is slow! Itaniums
|
||||
|
|
|
|||
|
|
@ -398,7 +398,8 @@ static void kretprobe_trampoline(void)
|
|||
|
||||
int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs)
|
||||
{
|
||||
regs->cr_iip = __kretprobe_trampoline_handler(regs, kretprobe_trampoline, NULL);
|
||||
regs->cr_iip = __kretprobe_trampoline_handler(regs,
|
||||
dereference_function_descriptor(kretprobe_trampoline), NULL);
|
||||
/*
|
||||
* By returning a non-zero value, we are telling
|
||||
* kprobe_handler() that we don't want the post_handler
|
||||
|
|
@ -414,7 +415,7 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
|
|||
ri->fp = NULL;
|
||||
|
||||
/* Replace the return addr with trampoline addr */
|
||||
regs->b0 = ((struct fnptr *)kretprobe_trampoline)->ip;
|
||||
regs->b0 = (unsigned long)dereference_function_descriptor(kretprobe_trampoline);
|
||||
}
|
||||
|
||||
/* Check the instruction in the slot is break */
|
||||
|
|
@ -918,14 +919,14 @@ static struct kprobe trampoline_p = {
|
|||
int __init arch_init_kprobes(void)
|
||||
{
|
||||
trampoline_p.addr =
|
||||
(kprobe_opcode_t *)((struct fnptr *)kretprobe_trampoline)->ip;
|
||||
dereference_function_descriptor(kretprobe_trampoline);
|
||||
return register_kprobe(&trampoline_p);
|
||||
}
|
||||
|
||||
int __kprobes arch_trampoline_kprobe(struct kprobe *p)
|
||||
{
|
||||
if (p->addr ==
|
||||
(kprobe_opcode_t *)((struct fnptr *)kretprobe_trampoline)->ip)
|
||||
dereference_function_descriptor(kretprobe_trampoline))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ source "drivers/zorro/Kconfig"
|
|||
|
||||
endif
|
||||
|
||||
if !MMU
|
||||
if COLDFIRE
|
||||
|
||||
config ISA_DMA_API
|
||||
def_bool !M5272
|
||||
|
|
|
|||
|
|
@ -190,6 +190,7 @@ config INIT_LCD
|
|||
config MEMORY_RESERVE
|
||||
int "Memory reservation (MiB)"
|
||||
depends on (UCSIMM || UCDIMM)
|
||||
default 0
|
||||
help
|
||||
Reserve certain memory regions on 68x328 based boards.
|
||||
|
||||
|
|
|
|||
|
|
@ -17,21 +17,21 @@
|
|||
* two accesses to memory, which may be undesirable for some devices.
|
||||
*/
|
||||
#define in_8(addr) \
|
||||
({ u8 __v = (*(__force volatile u8 *) (addr)); __v; })
|
||||
({ u8 __v = (*(__force volatile u8 *) (unsigned long)(addr)); __v; })
|
||||
#define in_be16(addr) \
|
||||
({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
|
||||
({ u16 __v = (*(__force volatile u16 *) (unsigned long)(addr)); __v; })
|
||||
#define in_be32(addr) \
|
||||
({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
|
||||
({ u32 __v = (*(__force volatile u32 *) (unsigned long)(addr)); __v; })
|
||||
#define in_le16(addr) \
|
||||
({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; })
|
||||
({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (unsigned long)(addr)); __v; })
|
||||
#define in_le32(addr) \
|
||||
({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; })
|
||||
({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (unsigned long)(addr)); __v; })
|
||||
|
||||
#define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b))
|
||||
#define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w))
|
||||
#define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l))
|
||||
#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w))
|
||||
#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l))
|
||||
#define out_8(addr,b) (void)((*(__force volatile u8 *) (unsigned long)(addr)) = (b))
|
||||
#define out_be16(addr,w) (void)((*(__force volatile u16 *) (unsigned long)(addr)) = (w))
|
||||
#define out_be32(addr,l) (void)((*(__force volatile u32 *) (unsigned long)(addr)) = (l))
|
||||
#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (unsigned long)(addr)) = cpu_to_le16(w))
|
||||
#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (unsigned long)(addr)) = cpu_to_le32(l))
|
||||
|
||||
#define raw_inb in_8
|
||||
#define raw_inw in_be16
|
||||
|
|
|
|||
|
|
@ -448,7 +448,7 @@ static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
|
|||
|
||||
if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
|
||||
fpu_version = sc->sc_fpstate[0];
|
||||
if (CPU_IS_020_OR_030 &&
|
||||
if (CPU_IS_020_OR_030 && !regs->stkadj &&
|
||||
regs->vector >= (VEC_FPBRUC * 4) &&
|
||||
regs->vector <= (VEC_FPNAN * 4)) {
|
||||
/* Clear pending exception in 68882 idle frame */
|
||||
|
|
@ -511,7 +511,7 @@ static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *
|
|||
if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
|
||||
context_size = fpstate[1];
|
||||
fpu_version = fpstate[0];
|
||||
if (CPU_IS_020_OR_030 &&
|
||||
if (CPU_IS_020_OR_030 && !regs->stkadj &&
|
||||
regs->vector >= (VEC_FPBRUC * 4) &&
|
||||
regs->vector <= (VEC_FPNAN * 4)) {
|
||||
/* Clear pending exception in 68882 idle frame */
|
||||
|
|
@ -829,18 +829,24 @@ badframe:
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline struct pt_regs *rte_regs(struct pt_regs *regs)
|
||||
{
|
||||
return (void *)regs + regs->stkadj;
|
||||
}
|
||||
|
||||
static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
|
||||
unsigned long mask)
|
||||
{
|
||||
struct pt_regs *tregs = rte_regs(regs);
|
||||
sc->sc_mask = mask;
|
||||
sc->sc_usp = rdusp();
|
||||
sc->sc_d0 = regs->d0;
|
||||
sc->sc_d1 = regs->d1;
|
||||
sc->sc_a0 = regs->a0;
|
||||
sc->sc_a1 = regs->a1;
|
||||
sc->sc_sr = regs->sr;
|
||||
sc->sc_pc = regs->pc;
|
||||
sc->sc_formatvec = regs->format << 12 | regs->vector;
|
||||
sc->sc_sr = tregs->sr;
|
||||
sc->sc_pc = tregs->pc;
|
||||
sc->sc_formatvec = tregs->format << 12 | tregs->vector;
|
||||
save_a5_state(sc, regs);
|
||||
save_fpu_state(sc, regs);
|
||||
}
|
||||
|
|
@ -848,6 +854,7 @@ static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
|
|||
static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
|
||||
{
|
||||
struct switch_stack *sw = (struct switch_stack *)regs - 1;
|
||||
struct pt_regs *tregs = rte_regs(regs);
|
||||
greg_t __user *gregs = uc->uc_mcontext.gregs;
|
||||
int err = 0;
|
||||
|
||||
|
|
@ -868,9 +875,9 @@ static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *
|
|||
err |= __put_user(sw->a5, &gregs[13]);
|
||||
err |= __put_user(sw->a6, &gregs[14]);
|
||||
err |= __put_user(rdusp(), &gregs[15]);
|
||||
err |= __put_user(regs->pc, &gregs[16]);
|
||||
err |= __put_user(regs->sr, &gregs[17]);
|
||||
err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec);
|
||||
err |= __put_user(tregs->pc, &gregs[16]);
|
||||
err |= __put_user(tregs->sr, &gregs[17]);
|
||||
err |= __put_user((tregs->format << 12) | tregs->vector, &uc->uc_formatvec);
|
||||
err |= rt_save_fpu_state(uc, regs);
|
||||
return err;
|
||||
}
|
||||
|
|
@ -887,13 +894,14 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set,
|
|||
struct pt_regs *regs)
|
||||
{
|
||||
struct sigframe __user *frame;
|
||||
int fsize = frame_extra_sizes(regs->format);
|
||||
struct pt_regs *tregs = rte_regs(regs);
|
||||
int fsize = frame_extra_sizes(tregs->format);
|
||||
struct sigcontext context;
|
||||
int err = 0, sig = ksig->sig;
|
||||
|
||||
if (fsize < 0) {
|
||||
pr_debug("setup_frame: Unknown frame format %#x\n",
|
||||
regs->format);
|
||||
tregs->format);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
|
|
@ -904,7 +912,7 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set,
|
|||
|
||||
err |= __put_user(sig, &frame->sig);
|
||||
|
||||
err |= __put_user(regs->vector, &frame->code);
|
||||
err |= __put_user(tregs->vector, &frame->code);
|
||||
err |= __put_user(&frame->sc, &frame->psc);
|
||||
|
||||
if (_NSIG_WORDS > 1)
|
||||
|
|
@ -929,34 +937,28 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set,
|
|||
|
||||
push_cache ((unsigned long) &frame->retcode);
|
||||
|
||||
/*
|
||||
* Set up registers for signal handler. All the state we are about
|
||||
* to destroy is successfully copied to sigframe.
|
||||
*/
|
||||
wrusp ((unsigned long) frame);
|
||||
regs->pc = (unsigned long) ksig->ka.sa.sa_handler;
|
||||
adjustformat(regs);
|
||||
|
||||
/*
|
||||
* This is subtle; if we build more than one sigframe, all but the
|
||||
* first one will see frame format 0 and have fsize == 0, so we won't
|
||||
* screw stkadj.
|
||||
*/
|
||||
if (fsize)
|
||||
if (fsize) {
|
||||
regs->stkadj = fsize;
|
||||
|
||||
/* Prepare to skip over the extra stuff in the exception frame. */
|
||||
if (regs->stkadj) {
|
||||
struct pt_regs *tregs =
|
||||
(struct pt_regs *)((ulong)regs + regs->stkadj);
|
||||
tregs = rte_regs(regs);
|
||||
pr_debug("Performing stackadjust=%04lx\n", regs->stkadj);
|
||||
/* This must be copied with decreasing addresses to
|
||||
handle overlaps. */
|
||||
tregs->vector = 0;
|
||||
tregs->format = 0;
|
||||
tregs->pc = regs->pc;
|
||||
tregs->sr = regs->sr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up registers for signal handler. All the state we are about
|
||||
* to destroy is successfully copied to sigframe.
|
||||
*/
|
||||
wrusp ((unsigned long) frame);
|
||||
tregs->pc = (unsigned long) ksig->ka.sa.sa_handler;
|
||||
adjustformat(regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -964,7 +966,8 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
|
|||
struct pt_regs *regs)
|
||||
{
|
||||
struct rt_sigframe __user *frame;
|
||||
int fsize = frame_extra_sizes(regs->format);
|
||||
struct pt_regs *tregs = rte_regs(regs);
|
||||
int fsize = frame_extra_sizes(tregs->format);
|
||||
int err = 0, sig = ksig->sig;
|
||||
|
||||
if (fsize < 0) {
|
||||
|
|
@ -1013,34 +1016,27 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
|
|||
|
||||
push_cache ((unsigned long) &frame->retcode);
|
||||
|
||||
/*
|
||||
* Set up registers for signal handler. All the state we are about
|
||||
* to destroy is successfully copied to sigframe.
|
||||
*/
|
||||
wrusp ((unsigned long) frame);
|
||||
regs->pc = (unsigned long) ksig->ka.sa.sa_handler;
|
||||
adjustformat(regs);
|
||||
|
||||
/*
|
||||
* This is subtle; if we build more than one sigframe, all but the
|
||||
* first one will see frame format 0 and have fsize == 0, so we won't
|
||||
* screw stkadj.
|
||||
*/
|
||||
if (fsize)
|
||||
if (fsize) {
|
||||
regs->stkadj = fsize;
|
||||
|
||||
/* Prepare to skip over the extra stuff in the exception frame. */
|
||||
if (regs->stkadj) {
|
||||
struct pt_regs *tregs =
|
||||
(struct pt_regs *)((ulong)regs + regs->stkadj);
|
||||
tregs = rte_regs(regs);
|
||||
pr_debug("Performing stackadjust=%04lx\n", regs->stkadj);
|
||||
/* This must be copied with decreasing addresses to
|
||||
handle overlaps. */
|
||||
tregs->vector = 0;
|
||||
tregs->format = 0;
|
||||
tregs->pc = regs->pc;
|
||||
tregs->sr = regs->sr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up registers for signal handler. All the state we are about
|
||||
* to destroy is successfully copied to sigframe.
|
||||
*/
|
||||
wrusp ((unsigned long) frame);
|
||||
tregs->pc = (unsigned long) ksig->ka.sa.sa_handler;
|
||||
adjustformat(regs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ config MIPS
|
|||
select HAVE_ARCH_TRACEHOOK
|
||||
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
|
||||
select HAVE_ASM_MODVERSIONS
|
||||
select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
|
||||
select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
|
||||
select HAVE_CONTEXT_TRACKING
|
||||
select HAVE_COPY_THREAD_TLS
|
||||
|
|
@ -1392,6 +1393,7 @@ config CPU_LOONGSON3
|
|||
select WEAK_REORDERING_BEYOND_LLSC
|
||||
select MIPS_PGD_C0_CONTEXT
|
||||
select MIPS_L1_CACHE_SHIFT_6
|
||||
select MIPS_FP_SUPPORT
|
||||
select GPIOLIB
|
||||
select SWIOTLB
|
||||
help
|
||||
|
|
|
|||
|
|
@ -239,6 +239,7 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
|
|||
" .set " MIPS_ISA_ARCH_LEVEL " \n"
|
||||
/* Load 64 bits from ptr */
|
||||
"1: lld %L0, %3 # __cmpxchg64 \n"
|
||||
" .set pop \n"
|
||||
/*
|
||||
* Split the 64 bit value we loaded into the 2 registers that hold the
|
||||
* ret variable.
|
||||
|
|
@ -266,6 +267,8 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
|
|||
" or %L1, %L1, $at \n"
|
||||
" .set at \n"
|
||||
# endif
|
||||
" .set push \n"
|
||||
" .set " MIPS_ISA_ARCH_LEVEL " \n"
|
||||
/* Attempt to store new at ptr */
|
||||
" scd %L1, %2 \n"
|
||||
/* If we failed, loop! */
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#ifndef __MIPS_ASM_MIPS_CM_H__
|
||||
#define __MIPS_ASM_MIPS_CM_H__
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
|
|
@ -153,8 +154,8 @@ GCR_ACCESSOR_RO(32, 0x030, rev)
|
|||
#define CM_GCR_REV_MINOR GENMASK(7, 0)
|
||||
|
||||
#define CM_ENCODE_REV(major, minor) \
|
||||
(((major) << __ffs(CM_GCR_REV_MAJOR)) | \
|
||||
((minor) << __ffs(CM_GCR_REV_MINOR)))
|
||||
(FIELD_PREP(CM_GCR_REV_MAJOR, major) | \
|
||||
FIELD_PREP(CM_GCR_REV_MINOR, minor))
|
||||
|
||||
#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
|
||||
#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
|
||||
|
|
@ -362,10 +363,10 @@ static inline int mips_cm_revision(void)
|
|||
static inline unsigned int mips_cm_max_vp_width(void)
|
||||
{
|
||||
extern int smp_num_siblings;
|
||||
uint32_t cfg;
|
||||
|
||||
if (mips_cm_revision() >= CM_REV_CM3)
|
||||
return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
|
||||
return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW,
|
||||
read_gcr_sys_config2());
|
||||
|
||||
if (mips_cm_present()) {
|
||||
/*
|
||||
|
|
@ -373,8 +374,7 @@ static inline unsigned int mips_cm_max_vp_width(void)
|
|||
* number of VP(E)s, and if that ever changes then this will
|
||||
* need revisiting.
|
||||
*/
|
||||
cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
|
||||
return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
|
||||
return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1;
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SMP))
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ do { \
|
|||
leaf++; \
|
||||
} while (0)
|
||||
|
||||
static int __init_cache_level(unsigned int cpu)
|
||||
int init_cache_level(unsigned int cpu)
|
||||
{
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
|
@ -69,7 +69,7 @@ static void fill_cpumask_cluster(int cpu, cpumask_t *cpu_map)
|
|||
cpumask_set_cpu(cpu1, cpu_map);
|
||||
}
|
||||
|
||||
static int __populate_cache_leaves(unsigned int cpu)
|
||||
int populate_cache_leaves(unsigned int cpu)
|
||||
{
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
|
@ -98,6 +98,3 @@ static int __populate_cache_leaves(unsigned int cpu)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
|
||||
DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
|
||||
|
|
|
|||
|
|
@ -179,8 +179,7 @@ static void mips_cm_probe_l2sync(void)
|
|||
phys_addr_t addr;
|
||||
|
||||
/* L2-only sync was introduced with CM major revision 6 */
|
||||
major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR) >>
|
||||
__ffs(CM_GCR_REV_MAJOR);
|
||||
major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev());
|
||||
if (major_rev < 6)
|
||||
return;
|
||||
|
||||
|
|
@ -263,13 +262,13 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core,
|
|||
preempt_disable();
|
||||
|
||||
if (cm_rev >= CM_REV_CM3) {
|
||||
val = core << __ffs(CM3_GCR_Cx_OTHER_CORE);
|
||||
val |= vp << __ffs(CM3_GCR_Cx_OTHER_VP);
|
||||
val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) |
|
||||
FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
|
||||
|
||||
if (cm_rev >= CM_REV_CM3_5) {
|
||||
val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
|
||||
val |= cluster << __ffs(CM_GCR_Cx_OTHER_CLUSTER);
|
||||
val |= block << __ffs(CM_GCR_Cx_OTHER_BLOCK);
|
||||
val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
|
||||
val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
|
||||
} else {
|
||||
WARN_ON(cluster != 0);
|
||||
WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
|
||||
|
|
@ -299,7 +298,7 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core,
|
|||
spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
|
||||
per_cpu(cm_core_lock_flags, curr_core));
|
||||
|
||||
val = core << __ffs(CM_GCR_Cx_OTHER_CORENUM);
|
||||
val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
|
||||
}
|
||||
|
||||
write_gcr_cl_other(val);
|
||||
|
|
@ -343,8 +342,8 @@ void mips_cm_error_report(void)
|
|||
cm_other = read_gcr_error_mult();
|
||||
|
||||
if (revision < CM_REV_CM3) { /* CM2 */
|
||||
cause = cm_error >> __ffs(CM_GCR_ERROR_CAUSE_ERRTYPE);
|
||||
ocause = cm_other >> __ffs(CM_GCR_ERROR_MULT_ERR2ND);
|
||||
cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
|
||||
ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
|
||||
|
||||
if (!cause)
|
||||
return;
|
||||
|
|
@ -386,8 +385,8 @@ void mips_cm_error_report(void)
|
|||
ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
|
||||
ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
|
||||
|
||||
cause = cm_error >> __ffs64(CM3_GCR_ERROR_CAUSE_ERRTYPE);
|
||||
ocause = cm_other >> __ffs(CM_GCR_ERROR_MULT_ERR2ND);
|
||||
cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
|
||||
ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
|
||||
|
||||
if (!cause)
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@
|
|||
#define EX2(a,b) \
|
||||
9: a,##b; \
|
||||
.section __ex_table,"a"; \
|
||||
PTR 9b,bad_stack; \
|
||||
PTR 9b+4,bad_stack; \
|
||||
PTR 9b,fault; \
|
||||
PTR 9b+4,fault; \
|
||||
.previous
|
||||
|
||||
.set mips1
|
||||
|
|
|
|||
|
|
@ -239,12 +239,3 @@ SYSCALL_DEFINE3(cachectl, char *, addr, int, nbytes, int, op)
|
|||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we ever come here the user sp is bad. Zap the process right away.
|
||||
* Due to the bad stack signaling wouldn't work.
|
||||
*/
|
||||
asmlinkage void bad_stack(void)
|
||||
{
|
||||
do_exit(SIGSEGV);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/export.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
@ -29,6 +30,7 @@
|
|||
#define LTQ_DMA_PCTRL 0x44
|
||||
#define LTQ_DMA_IRNEN 0xf4
|
||||
|
||||
#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
|
||||
#define DMA_DESCPT BIT(3) /* descriptor complete irq */
|
||||
#define DMA_TX BIT(8) /* TX channel direction */
|
||||
#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
|
||||
|
|
@ -39,7 +41,6 @@
|
|||
#define DMA_POLL BIT(31) /* turn on channel polling */
|
||||
#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
|
||||
#define DMA_2W_BURST BIT(1) /* 2 word burst length */
|
||||
#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
|
||||
#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
|
||||
#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
|
||||
|
||||
|
|
@ -205,7 +206,7 @@ ltq_dma_init(struct platform_device *pdev)
|
|||
{
|
||||
struct clk *clk;
|
||||
struct resource *res;
|
||||
unsigned id;
|
||||
unsigned int id, nchannels;
|
||||
int i;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
|
@ -221,21 +222,24 @@ ltq_dma_init(struct platform_device *pdev)
|
|||
clk_enable(clk);
|
||||
ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
|
||||
|
||||
usleep_range(1, 10);
|
||||
|
||||
/* disable all interrupts */
|
||||
ltq_dma_w32(0, LTQ_DMA_IRNEN);
|
||||
|
||||
/* reset/configure each channel */
|
||||
for (i = 0; i < DMA_MAX_CHANNEL; i++) {
|
||||
id = ltq_dma_r32(LTQ_DMA_ID);
|
||||
nchannels = ((id & DMA_ID_CHNR) >> 20);
|
||||
for (i = 0; i < nchannels; i++) {
|
||||
ltq_dma_w32(i, LTQ_DMA_CS);
|
||||
ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
|
||||
ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
|
||||
ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
|
||||
}
|
||||
|
||||
id = ltq_dma_r32(LTQ_DMA_ID);
|
||||
dev_info(&pdev->dev,
|
||||
"Init done - hw rev: %X, ports: %d, channels: %d\n",
|
||||
id & 0x1f, (id >> 16) & 0xf, id >> 20);
|
||||
id & 0x1f, (id >> 16) & 0xf, nchannels);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
#define ROCIT_CONFIG_GEN1_MEMMAP_SHIFT 8
|
||||
#define ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8)
|
||||
|
||||
static unsigned char fdt_buf[16 << 10] __initdata;
|
||||
static unsigned char fdt_buf[16 << 10] __initdata __aligned(8);
|
||||
|
||||
/* determined physical memory size, not overridden by command line args */
|
||||
extern unsigned long physical_memsize;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# MIPS networking code
|
||||
|
||||
obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o
|
||||
obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o
|
||||
|
|
|
|||
1299
arch/mips/net/bpf_jit.c
Normal file
1299
arch/mips/net/bpf_jit.c
Normal file
File diff suppressed because it is too large
Load diff
285
arch/mips/net/bpf_jit_asm.S
Normal file
285
arch/mips/net/bpf_jit_asm.S
Normal file
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* bpf_jib_asm.S: Packet/header access helper functions for MIPS/MIPS64 BPF
|
||||
* compiler.
|
||||
*
|
||||
* Copyright (C) 2015 Imagination Technologies Ltd.
|
||||
* Author: Markos Chandras <markos.chandras@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/isa-rev.h>
|
||||
#include <asm/regdef.h>
|
||||
#include "bpf_jit.h"
|
||||
|
||||
/* ABI
|
||||
*
|
||||
* r_skb_hl skb header length
|
||||
* r_skb_data skb data
|
||||
* r_off(a1) offset register
|
||||
* r_A BPF register A
|
||||
* r_X PF register X
|
||||
* r_skb(a0) *skb
|
||||
* r_M *scratch memory
|
||||
* r_skb_le skb length
|
||||
* r_s0 Scratch register 0
|
||||
* r_s1 Scratch register 1
|
||||
*
|
||||
* On entry:
|
||||
* a0: *skb
|
||||
* a1: offset (imm or imm + X)
|
||||
*
|
||||
* All non-BPF-ABI registers are free for use. On return, we only
|
||||
* care about r_ret. The BPF-ABI registers are assumed to remain
|
||||
* unmodified during the entire filter operation.
|
||||
*/
|
||||
|
||||
#define skb a0
|
||||
#define offset a1
|
||||
#define SKF_LL_OFF (-0x200000) /* Can't include linux/filter.h in assembly */
|
||||
|
||||
/* We know better :) so prevent assembler reordering etc */
|
||||
.set noreorder
|
||||
|
||||
#define is_offset_negative(TYPE) \
|
||||
/* If offset is negative we have more work to do */ \
|
||||
slti t0, offset, 0; \
|
||||
bgtz t0, bpf_slow_path_##TYPE##_neg; \
|
||||
/* Be careful what follows in DS. */
|
||||
|
||||
#define is_offset_in_header(SIZE, TYPE) \
|
||||
/* Reading from header? */ \
|
||||
addiu $r_s0, $r_skb_hl, -SIZE; \
|
||||
slt t0, $r_s0, offset; \
|
||||
bgtz t0, bpf_slow_path_##TYPE; \
|
||||
|
||||
LEAF(sk_load_word)
|
||||
is_offset_negative(word)
|
||||
FEXPORT(sk_load_word_positive)
|
||||
is_offset_in_header(4, word)
|
||||
/* Offset within header boundaries */
|
||||
PTR_ADDU t1, $r_skb_data, offset
|
||||
.set reorder
|
||||
lw $r_A, 0(t1)
|
||||
.set noreorder
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if MIPS_ISA_REV >= 2
|
||||
wsbh t0, $r_A
|
||||
rotr $r_A, t0, 16
|
||||
# else
|
||||
sll t0, $r_A, 24
|
||||
srl t1, $r_A, 24
|
||||
srl t2, $r_A, 8
|
||||
or t0, t0, t1
|
||||
andi t2, t2, 0xff00
|
||||
andi t1, $r_A, 0xff00
|
||||
or t0, t0, t2
|
||||
sll t1, t1, 8
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#endif
|
||||
jr $r_ra
|
||||
move $r_ret, zero
|
||||
END(sk_load_word)
|
||||
|
||||
LEAF(sk_load_half)
|
||||
is_offset_negative(half)
|
||||
FEXPORT(sk_load_half_positive)
|
||||
is_offset_in_header(2, half)
|
||||
/* Offset within header boundaries */
|
||||
PTR_ADDU t1, $r_skb_data, offset
|
||||
lhu $r_A, 0(t1)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if MIPS_ISA_REV >= 2
|
||||
wsbh $r_A, $r_A
|
||||
# else
|
||||
sll t0, $r_A, 8
|
||||
srl t1, $r_A, 8
|
||||
andi t0, t0, 0xff00
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#endif
|
||||
jr $r_ra
|
||||
move $r_ret, zero
|
||||
END(sk_load_half)
|
||||
|
||||
LEAF(sk_load_byte)
|
||||
is_offset_negative(byte)
|
||||
FEXPORT(sk_load_byte_positive)
|
||||
is_offset_in_header(1, byte)
|
||||
/* Offset within header boundaries */
|
||||
PTR_ADDU t1, $r_skb_data, offset
|
||||
lbu $r_A, 0(t1)
|
||||
jr $r_ra
|
||||
move $r_ret, zero
|
||||
END(sk_load_byte)
|
||||
|
||||
/*
|
||||
* call skb_copy_bits:
|
||||
* (prototype in linux/skbuff.h)
|
||||
*
|
||||
* int skb_copy_bits(sk_buff *skb, int offset, void *to, int len)
|
||||
*
|
||||
* o32 mandates we leave 4 spaces for argument registers in case
|
||||
* the callee needs to use them. Even though we don't care about
|
||||
* the argument registers ourselves, we need to allocate that space
|
||||
* to remain ABI compliant since the callee may want to use that space.
|
||||
* We also allocate 2 more spaces for $r_ra and our return register (*to).
|
||||
*
|
||||
* n64 is a bit different. The *caller* will allocate the space to preserve
|
||||
* the arguments. So in 64-bit kernels, we allocate the 4-arg space for no
|
||||
* good reason but it does not matter that much really.
|
||||
*
|
||||
* (void *to) is returned in r_s0
|
||||
*
|
||||
*/
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
#define DS_OFFSET(SIZE) (4 * SZREG)
|
||||
#else
|
||||
#define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE))
|
||||
#endif
|
||||
#define bpf_slow_path_common(SIZE) \
|
||||
/* Quick check. Are we within reasonable boundaries? */ \
|
||||
LONG_ADDIU $r_s1, $r_skb_len, -SIZE; \
|
||||
sltu $r_s0, offset, $r_s1; \
|
||||
beqz $r_s0, fault; \
|
||||
/* Load 4th argument in DS */ \
|
||||
LONG_ADDIU a3, zero, SIZE; \
|
||||
PTR_ADDIU $r_sp, $r_sp, -(6 * SZREG); \
|
||||
PTR_LA t0, skb_copy_bits; \
|
||||
PTR_S $r_ra, (5 * SZREG)($r_sp); \
|
||||
/* Assign low slot to a2 */ \
|
||||
PTR_ADDIU a2, $r_sp, DS_OFFSET(SIZE); \
|
||||
jalr t0; \
|
||||
/* Reset our destination slot (DS but it's ok) */ \
|
||||
INT_S zero, (4 * SZREG)($r_sp); \
|
||||
/* \
|
||||
* skb_copy_bits returns 0 on success and -EFAULT \
|
||||
* on error. Our data live in a2. Do not bother with \
|
||||
* our data if an error has been returned. \
|
||||
*/ \
|
||||
/* Restore our frame */ \
|
||||
PTR_L $r_ra, (5 * SZREG)($r_sp); \
|
||||
INT_L $r_s0, (4 * SZREG)($r_sp); \
|
||||
bltz v0, fault; \
|
||||
PTR_ADDIU $r_sp, $r_sp, 6 * SZREG; \
|
||||
move $r_ret, zero; \
|
||||
|
||||
NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(4)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if MIPS_ISA_REV >= 2
|
||||
wsbh t0, $r_s0
|
||||
jr $r_ra
|
||||
rotr $r_A, t0, 16
|
||||
# else
|
||||
sll t0, $r_s0, 24
|
||||
srl t1, $r_s0, 24
|
||||
srl t2, $r_s0, 8
|
||||
or t0, t0, t1
|
||||
andi t2, t2, 0xff00
|
||||
andi t1, $r_s0, 0xff00
|
||||
or t0, t0, t2
|
||||
sll t1, t1, 8
|
||||
jr $r_ra
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#else
|
||||
jr $r_ra
|
||||
move $r_A, $r_s0
|
||||
#endif
|
||||
|
||||
END(bpf_slow_path_word)
|
||||
|
||||
NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(2)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if MIPS_ISA_REV >= 2
|
||||
jr $r_ra
|
||||
wsbh $r_A, $r_s0
|
||||
# else
|
||||
sll t0, $r_s0, 8
|
||||
andi t1, $r_s0, 0xff00
|
||||
andi t0, t0, 0xff00
|
||||
srl t1, t1, 8
|
||||
jr $r_ra
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#else
|
||||
jr $r_ra
|
||||
move $r_A, $r_s0
|
||||
#endif
|
||||
|
||||
END(bpf_slow_path_half)
|
||||
|
||||
NESTED(bpf_slow_path_byte, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(1)
|
||||
jr $r_ra
|
||||
move $r_A, $r_s0
|
||||
|
||||
END(bpf_slow_path_byte)
|
||||
|
||||
/*
|
||||
* Negative entry points
|
||||
*/
|
||||
.macro bpf_is_end_of_data
|
||||
li t0, SKF_LL_OFF
|
||||
/* Reading link layer data? */
|
||||
slt t1, offset, t0
|
||||
bgtz t1, fault
|
||||
/* Be careful what follows in DS. */
|
||||
.endm
|
||||
/*
|
||||
* call skb_copy_bits:
|
||||
* (prototype in linux/filter.h)
|
||||
*
|
||||
* void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb,
|
||||
* int k, unsigned int size)
|
||||
*
|
||||
* see above (bpf_slow_path_common) for ABI restrictions
|
||||
*/
|
||||
#define bpf_negative_common(SIZE) \
|
||||
PTR_ADDIU $r_sp, $r_sp, -(6 * SZREG); \
|
||||
PTR_LA t0, bpf_internal_load_pointer_neg_helper; \
|
||||
PTR_S $r_ra, (5 * SZREG)($r_sp); \
|
||||
jalr t0; \
|
||||
li a2, SIZE; \
|
||||
PTR_L $r_ra, (5 * SZREG)($r_sp); \
|
||||
/* Check return pointer */ \
|
||||
beqz v0, fault; \
|
||||
PTR_ADDIU $r_sp, $r_sp, 6 * SZREG; \
|
||||
/* Preserve our pointer */ \
|
||||
move $r_s0, v0; \
|
||||
/* Set return value */ \
|
||||
move $r_ret, zero; \
|
||||
|
||||
bpf_slow_path_word_neg:
|
||||
bpf_is_end_of_data
|
||||
NESTED(sk_load_word_negative, (6 * SZREG), $r_sp)
|
||||
bpf_negative_common(4)
|
||||
jr $r_ra
|
||||
lw $r_A, 0($r_s0)
|
||||
END(sk_load_word_negative)
|
||||
|
||||
bpf_slow_path_half_neg:
|
||||
bpf_is_end_of_data
|
||||
NESTED(sk_load_half_negative, (6 * SZREG), $r_sp)
|
||||
bpf_negative_common(2)
|
||||
jr $r_ra
|
||||
lhu $r_A, 0($r_s0)
|
||||
END(sk_load_half_negative)
|
||||
|
||||
bpf_slow_path_byte_neg:
|
||||
bpf_is_end_of_data
|
||||
NESTED(sk_load_byte_negative, (6 * SZREG), $r_sp)
|
||||
bpf_negative_common(1)
|
||||
jr $r_ra
|
||||
lbu $r_A, 0($r_s0)
|
||||
END(sk_load_byte_negative)
|
||||
|
||||
fault:
|
||||
jr $r_ra
|
||||
addiu $r_ret, zero, 1
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
static inline unsigned long arch_local_save_flags(void)
|
||||
{
|
||||
return RDCTL(CTL_STATUS);
|
||||
return RDCTL(CTL_FSTATUS);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -18,7 +18,7 @@ static inline unsigned long arch_local_save_flags(void)
|
|||
*/
|
||||
static inline void arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
WRCTL(CTL_STATUS, flags);
|
||||
WRCTL(CTL_FSTATUS, flags);
|
||||
}
|
||||
|
||||
static inline void arch_local_irq_disable(void)
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#endif
|
||||
|
||||
/* control register numbers */
|
||||
#define CTL_STATUS 0
|
||||
#define CTL_FSTATUS 0
|
||||
#define CTL_ESTATUS 1
|
||||
#define CTL_BSTATUS 2
|
||||
#define CTL_IENABLE 3
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ config NIOS2_DTB_PHYS_ADDR
|
|||
|
||||
config NIOS2_DTB_SOURCE_BOOL
|
||||
bool "Compile and link device tree into kernel image"
|
||||
depends on !COMPILE_TEST
|
||||
help
|
||||
This allows you to specify a dts (device tree source) file
|
||||
which will be compiled and linked into the kernel image.
|
||||
|
|
|
|||
|
|
@ -547,6 +547,7 @@ EXCEPTION_ENTRY(_external_irq_handler)
|
|||
l.bnf 1f // ext irq enabled, all ok.
|
||||
l.nop
|
||||
|
||||
#ifdef CONFIG_PRINTK
|
||||
l.addi r1,r1,-0x8
|
||||
l.movhi r3,hi(42f)
|
||||
l.ori r3,r3,lo(42f)
|
||||
|
|
@ -560,6 +561,7 @@ EXCEPTION_ENTRY(_external_irq_handler)
|
|||
.string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
|
||||
.align 4
|
||||
.previous
|
||||
#endif
|
||||
|
||||
l.ori r4,r4,SPR_SR_IEE // fix the bug
|
||||
// l.sw PT_SR(r1),r4
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ extern int npmem_ranges;
|
|||
#include <asm-generic/getorder.h>
|
||||
#include <asm/pdc.h>
|
||||
|
||||
#define PAGE0 ((struct zeropage *)__PAGE_OFFSET)
|
||||
#define PAGE0 ((struct zeropage *)absolute_pointer(__PAGE_OFFSET))
|
||||
|
||||
/* DEFINITION OF THE ZERO-PAGE (PAG0) */
|
||||
/* based on work by Jason Eckhardt (jason@equator.com) */
|
||||
|
|
|
|||
|
|
@ -1841,8 +1841,8 @@ syscall_restore:
|
|||
LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
|
||||
|
||||
/* Are we being ptraced? */
|
||||
ldw TASK_FLAGS(%r1),%r19
|
||||
ldi _TIF_SYSCALL_TRACE_MASK,%r2
|
||||
LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
|
||||
ldi _TIF_SINGLESTEP|_TIF_BLOCKSTEP,%r2
|
||||
and,COND(=) %r19,%r2,%r0
|
||||
b,n syscall_restore_rfi
|
||||
|
||||
|
|
|
|||
|
|
@ -238,6 +238,12 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs,
|
|||
#endif
|
||||
|
||||
usp = (regs->gr[30] & ~(0x01UL));
|
||||
#ifdef CONFIG_64BIT
|
||||
if (is_compat_task()) {
|
||||
/* The gcc alloca implementation leaves garbage in the upper 32 bits of sp */
|
||||
usp = (compat_uint_t)usp;
|
||||
}
|
||||
#endif
|
||||
/*FIXME: frame_size parameter is unused, remove it. */
|
||||
frame = get_sigframe(&ksig->ka, usp, sizeof(*frame));
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/ftrace.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/kgdb.h>
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/current.h>
|
||||
|
|
@ -71,7 +72,10 @@ enum ipi_message_type {
|
|||
IPI_CALL_FUNC,
|
||||
IPI_CPU_START,
|
||||
IPI_CPU_STOP,
|
||||
IPI_CPU_TEST
|
||||
IPI_CPU_TEST,
|
||||
#ifdef CONFIG_KGDB
|
||||
IPI_ENTER_KGDB,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -169,7 +173,12 @@ ipi_interrupt(int irq, void *dev_id)
|
|||
case IPI_CPU_TEST:
|
||||
smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu);
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
case IPI_ENTER_KGDB:
|
||||
smp_debug(100, KERN_DEBUG "CPU%d ENTER_KGDB\n", this_cpu);
|
||||
kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printk(KERN_CRIT "Unknown IPI num on CPU%d: %lu\n",
|
||||
this_cpu, which);
|
||||
|
|
@ -225,6 +234,12 @@ send_IPI_allbutself(enum ipi_message_type op)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
void kgdb_roundup_cpus(void)
|
||||
{
|
||||
send_IPI_allbutself(IPI_ENTER_KGDB);
|
||||
}
|
||||
#endif
|
||||
|
||||
inline void
|
||||
smp_send_stop(void) { send_IPI_allbutself(IPI_CPU_STOP); }
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@
|
|||
#include <asm/ptrace.h>
|
||||
|
||||
#include <asm/unwind.h>
|
||||
#include <asm/switch_to.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
/* #define DEBUG 1 */
|
||||
#ifdef DEBUG
|
||||
|
|
@ -203,6 +205,11 @@ int __init unwind_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool pc_is_kernel_fn(unsigned long pc, void *fn)
|
||||
{
|
||||
return (unsigned long)dereference_kernel_function_descriptor(fn) == pc;
|
||||
}
|
||||
|
||||
static int unwind_special(struct unwind_frame_info *info, unsigned long pc, int frame_size)
|
||||
{
|
||||
/*
|
||||
|
|
@ -221,7 +228,7 @@ static int unwind_special(struct unwind_frame_info *info, unsigned long pc, int
|
|||
extern void * const _call_on_stack;
|
||||
#endif /* CONFIG_IRQSTACKS */
|
||||
|
||||
if (pc == (unsigned long) &handle_interruption) {
|
||||
if (pc_is_kernel_fn(pc, handle_interruption)) {
|
||||
struct pt_regs *regs = (struct pt_regs *)(info->sp - frame_size - PT_SZ_ALGN);
|
||||
dbg("Unwinding through handle_interruption()\n");
|
||||
info->prev_sp = regs->gr[30];
|
||||
|
|
@ -229,13 +236,13 @@ static int unwind_special(struct unwind_frame_info *info, unsigned long pc, int
|
|||
return 1;
|
||||
}
|
||||
|
||||
if (pc == (unsigned long) &ret_from_kernel_thread ||
|
||||
pc == (unsigned long) &syscall_exit) {
|
||||
if (pc_is_kernel_fn(pc, ret_from_kernel_thread) ||
|
||||
pc_is_kernel_fn(pc, syscall_exit)) {
|
||||
info->prev_sp = info->prev_ip = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (pc == (unsigned long) &intr_return) {
|
||||
if (pc_is_kernel_fn(pc, intr_return)) {
|
||||
struct pt_regs *regs;
|
||||
|
||||
dbg("Found intr_return()\n");
|
||||
|
|
@ -246,20 +253,20 @@ static int unwind_special(struct unwind_frame_info *info, unsigned long pc, int
|
|||
return 1;
|
||||
}
|
||||
|
||||
if (pc == (unsigned long) &_switch_to_ret) {
|
||||
if (pc_is_kernel_fn(pc, _switch_to) ||
|
||||
pc_is_kernel_fn(pc, _switch_to_ret)) {
|
||||
info->prev_sp = info->sp - CALLEE_SAVE_FRAME_SIZE;
|
||||
info->prev_ip = *(unsigned long *)(info->prev_sp - RP_OFFSET);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IRQSTACKS
|
||||
if (pc == (unsigned long) &_call_on_stack) {
|
||||
if (pc_is_kernel_fn(pc, _call_on_stack)) {
|
||||
info->prev_sp = *(unsigned long *)(info->sp - FRAME_SIZE - REG_SZ);
|
||||
info->prev_ip = *(unsigned long *)(info->sp - FRAME_SIZE - RP_OFFSET);
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -56,6 +56,8 @@ SECTIONS
|
|||
{
|
||||
. = KERNEL_BINARY_TEXT_START;
|
||||
|
||||
_stext = .; /* start of kernel text, includes init code & data */
|
||||
|
||||
__init_begin = .;
|
||||
HEAD_TEXT_SECTION
|
||||
MLONGCALL_DISCARD(INIT_TEXT_SECTION(8))
|
||||
|
|
@ -79,7 +81,6 @@ SECTIONS
|
|||
/* freed after init ends here */
|
||||
|
||||
_text = .; /* Text and read-only data */
|
||||
_stext = .;
|
||||
MLONGCALL_KEEP(INIT_TEXT_SECTION(8))
|
||||
.text ALIGN(PAGE_SIZE) : {
|
||||
TEXT_TEXT
|
||||
|
|
|
|||
|
|
@ -310,12 +310,15 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
r1 &= ~3;
|
||||
fpregs[t+3] = fpregs[r1+3];
|
||||
fpregs[t+2] = fpregs[r1+2];
|
||||
fallthrough;
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
fpregs[t] = fpregs[r1];
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 3: /* FABS */
|
||||
switch (fmt) {
|
||||
case 2: /* illegal */
|
||||
|
|
@ -325,13 +328,16 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
r1 &= ~3;
|
||||
fpregs[t+3] = fpregs[r1+3];
|
||||
fpregs[t+2] = fpregs[r1+2];
|
||||
fallthrough;
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
/* copy and clear sign bit */
|
||||
fpregs[t] = fpregs[r1] & 0x7fffffff;
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 6: /* FNEG */
|
||||
switch (fmt) {
|
||||
case 2: /* illegal */
|
||||
|
|
@ -341,13 +347,16 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
r1 &= ~3;
|
||||
fpregs[t+3] = fpregs[r1+3];
|
||||
fpregs[t+2] = fpregs[r1+2];
|
||||
fallthrough;
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
/* copy and invert sign bit */
|
||||
fpregs[t] = fpregs[r1] ^ 0x80000000;
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 7: /* FNEGABS */
|
||||
switch (fmt) {
|
||||
case 2: /* illegal */
|
||||
|
|
@ -357,13 +366,16 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
r1 &= ~3;
|
||||
fpregs[t+3] = fpregs[r1+3];
|
||||
fpregs[t+2] = fpregs[r1+2];
|
||||
fallthrough;
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
/* copy and set sign bit */
|
||||
fpregs[t] = fpregs[r1] | 0x80000000;
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 4: /* FSQRT */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -376,6 +388,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 5: /* FRND */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -389,7 +402,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
} /* end of switch (subop) */
|
||||
|
||||
BUG();
|
||||
case 1: /* class 1 */
|
||||
df = extru(ir,fpdfpos,2); /* get dest format */
|
||||
if ((df & 2) || (fmt & 2)) {
|
||||
|
|
@ -419,6 +432,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* dbl/dbl */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 1: /* FCNVXF */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -434,6 +448,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(dbl_to_dbl_fcnvxf(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 2: /* FCNVFX */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -449,6 +464,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(dbl_to_dbl_fcnvfx(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 3: /* FCNVFXT */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -464,6 +480,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 5: /* FCNVUF (PA2.0 only) */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -479,6 +496,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(dbl_to_dbl_fcnvuf(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 6: /* FCNVFU (PA2.0 only) */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -494,6 +512,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(dbl_to_dbl_fcnvfu(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 7: /* FCNVFUT (PA2.0 only) */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -509,10 +528,11 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
return(dbl_to_dbl_fcnvfut(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 4: /* undefined */
|
||||
return(MAJOR_0C_EXCP);
|
||||
} /* end of switch subop */
|
||||
|
||||
BUG();
|
||||
case 2: /* class 2 */
|
||||
fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS];
|
||||
r2 = extru(ir, fpr2pos, 5) * sizeof(double)/sizeof(u_int);
|
||||
|
|
@ -590,6 +610,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 1: /* FTEST */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -609,8 +630,10 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3:
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
} /* end of switch subop */
|
||||
} /* end of else for PA1.0 & PA1.1 */
|
||||
BUG();
|
||||
case 3: /* class 3 */
|
||||
r2 = extru(ir,fpr2pos,5) * sizeof(double)/sizeof(u_int);
|
||||
if (r2 == 0)
|
||||
|
|
@ -633,6 +656,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 1: /* FSUB */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -645,6 +669,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 2: /* FMPY */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -657,6 +682,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 3: /* FDIV */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -669,6 +695,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 4: /* FREM */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -681,6 +708,7 @@ decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[])
|
|||
case 3: /* quad not implemented */
|
||||
return(MAJOR_0C_EXCP);
|
||||
}
|
||||
BUG();
|
||||
} /* end of class 3 switch */
|
||||
} /* end of switch(class) */
|
||||
|
||||
|
|
@ -736,10 +764,12 @@ u_int fpregs[];
|
|||
return(MAJOR_0E_EXCP);
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
fpregs[t] = fpregs[r1];
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 3: /* FABS */
|
||||
switch (fmt) {
|
||||
case 2:
|
||||
|
|
@ -747,10 +777,12 @@ u_int fpregs[];
|
|||
return(MAJOR_0E_EXCP);
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
fpregs[t] = fpregs[r1] & 0x7fffffff;
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 6: /* FNEG */
|
||||
switch (fmt) {
|
||||
case 2:
|
||||
|
|
@ -758,10 +790,12 @@ u_int fpregs[];
|
|||
return(MAJOR_0E_EXCP);
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
fpregs[t] = fpregs[r1] ^ 0x80000000;
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 7: /* FNEGABS */
|
||||
switch (fmt) {
|
||||
case 2:
|
||||
|
|
@ -769,10 +803,12 @@ u_int fpregs[];
|
|||
return(MAJOR_0E_EXCP);
|
||||
case 1: /* double */
|
||||
fpregs[t+1] = fpregs[r1+1];
|
||||
fallthrough;
|
||||
case 0: /* single */
|
||||
fpregs[t] = fpregs[r1] | 0x80000000;
|
||||
return(NOEXCEPTION);
|
||||
}
|
||||
BUG();
|
||||
case 4: /* FSQRT */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -785,6 +821,7 @@ u_int fpregs[];
|
|||
case 3:
|
||||
return(MAJOR_0E_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 5: /* FRMD */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -798,7 +835,7 @@ u_int fpregs[];
|
|||
return(MAJOR_0E_EXCP);
|
||||
}
|
||||
} /* end of switch (subop */
|
||||
|
||||
BUG();
|
||||
case 1: /* class 1 */
|
||||
df = extru(ir,fpdfpos,2); /* get dest format */
|
||||
/*
|
||||
|
|
@ -826,6 +863,7 @@ u_int fpregs[];
|
|||
case 3: /* dbl/dbl */
|
||||
return(MAJOR_0E_EXCP);
|
||||
}
|
||||
BUG();
|
||||
case 1: /* FCNVXF */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -841,6 +879,7 @@ u_int fpregs[];
|
|||
return(dbl_to_dbl_fcnvxf(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 2: /* FCNVFX */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -856,6 +895,7 @@ u_int fpregs[];
|
|||
return(dbl_to_dbl_fcnvfx(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 3: /* FCNVFXT */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -871,6 +911,7 @@ u_int fpregs[];
|
|||
return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 5: /* FCNVUF (PA2.0 only) */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -886,6 +927,7 @@ u_int fpregs[];
|
|||
return(dbl_to_dbl_fcnvuf(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 6: /* FCNVFU (PA2.0 only) */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -901,6 +943,7 @@ u_int fpregs[];
|
|||
return(dbl_to_dbl_fcnvfu(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 7: /* FCNVFUT (PA2.0 only) */
|
||||
switch(fmt) {
|
||||
case 0: /* sgl/sgl */
|
||||
|
|
@ -916,9 +959,11 @@ u_int fpregs[];
|
|||
return(dbl_to_dbl_fcnvfut(&fpregs[r1],0,
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 4: /* undefined */
|
||||
return(MAJOR_0C_EXCP);
|
||||
} /* end of switch subop */
|
||||
BUG();
|
||||
case 2: /* class 2 */
|
||||
/*
|
||||
* Be careful out there.
|
||||
|
|
@ -994,6 +1039,7 @@ u_int fpregs[];
|
|||
}
|
||||
} /* end of switch subop */
|
||||
} /* end of else for PA1.0 & PA1.1 */
|
||||
BUG();
|
||||
case 3: /* class 3 */
|
||||
/*
|
||||
* Be careful out there.
|
||||
|
|
@ -1026,6 +1072,7 @@ u_int fpregs[];
|
|||
return(dbl_fadd(&fpregs[r1],&fpregs[r2],
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 1: /* FSUB */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -1035,6 +1082,7 @@ u_int fpregs[];
|
|||
return(dbl_fsub(&fpregs[r1],&fpregs[r2],
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 2: /* FMPY or XMPYU */
|
||||
/*
|
||||
* check for integer multiply (x bit set)
|
||||
|
|
@ -1071,6 +1119,7 @@ u_int fpregs[];
|
|||
&fpregs[r2],&fpregs[t],status));
|
||||
}
|
||||
}
|
||||
BUG();
|
||||
case 3: /* FDIV */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
@ -1080,6 +1129,7 @@ u_int fpregs[];
|
|||
return(dbl_fdiv(&fpregs[r1],&fpregs[r2],
|
||||
&fpregs[t],status));
|
||||
}
|
||||
BUG();
|
||||
case 4: /* FREM */
|
||||
switch (fmt) {
|
||||
case 0:
|
||||
|
|
|
|||
|
|
@ -18,12 +18,9 @@ void notrace set_fixmap(enum fixed_addresses idx, phys_addr_t phys)
|
|||
pte_t *pte;
|
||||
|
||||
if (pmd_none(*pmd))
|
||||
pmd = pmd_alloc(NULL, pgd, vaddr);
|
||||
|
||||
pte = pte_offset_kernel(pmd, vaddr);
|
||||
if (pte_none(*pte))
|
||||
pte = pte_alloc_kernel(pmd, vaddr);
|
||||
|
||||
pte = pte_offset_kernel(pmd, vaddr);
|
||||
set_pte_at(&init_mm, vaddr, pte, __mk_pte(phys, PAGE_KERNEL_RWX));
|
||||
flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -892,9 +892,9 @@ void flush_tlb_all(void)
|
|||
{
|
||||
int do_recycle;
|
||||
|
||||
__inc_irq_stat(irq_tlb_count);
|
||||
do_recycle = 0;
|
||||
spin_lock(&sid_lock);
|
||||
__inc_irq_stat(irq_tlb_count);
|
||||
if (dirty_space_ids > RECYCLE_THRESHOLD) {
|
||||
BUG_ON(recycle_inuse); /* FIXME: Use a semaphore/wait queue here */
|
||||
get_dirty_sids(&recycle_ndirty,recycle_dirty_array);
|
||||
|
|
@ -913,8 +913,8 @@ void flush_tlb_all(void)
|
|||
#else
|
||||
void flush_tlb_all(void)
|
||||
{
|
||||
__inc_irq_stat(irq_tlb_count);
|
||||
spin_lock(&sid_lock);
|
||||
__inc_irq_stat(irq_tlb_count);
|
||||
flush_tlb_all_local(NULL);
|
||||
recycle_sids();
|
||||
spin_unlock(&sid_lock);
|
||||
|
|
|
|||
|
|
@ -154,7 +154,7 @@
|
|||
|
||||
fm1mac3: ethernet@e4000 {
|
||||
phy-handle = <&sgmii_aqr_phy3>;
|
||||
phy-connection-type = "sgmii-2500";
|
||||
phy-connection-type = "2500base-x";
|
||||
sleep = <&rcpm 0x20000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
|
|||
# CONFIG_MTD_CFI_I2 is not set
|
||||
CONFIG_MTD_CFI_I4=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#define BRANCH_ABSOLUTE 0x2
|
||||
|
||||
bool is_offset_in_branch_range(long offset);
|
||||
bool is_offset_in_cond_branch_range(long offset);
|
||||
unsigned int create_branch(const unsigned int *addr,
|
||||
unsigned long target, int flags);
|
||||
unsigned int create_cond_branch(const unsigned int *addr,
|
||||
|
|
|
|||
|
|
@ -34,6 +34,13 @@ static inline void ppc_set_pmu_inuse(int inuse)
|
|||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
|
||||
static inline int ppc_get_pmu_inuse(void)
|
||||
{
|
||||
return get_paca()->pmcregs_in_use;
|
||||
}
|
||||
#endif
|
||||
|
||||
extern void power4_enable_pmcs(void);
|
||||
|
||||
#else /* CONFIG_PPC64 */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue