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usb: dwc3: Disable USB2 internal retry for USB3.1 cores v1.70a and above

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STAR 9001346572 affects dwc_usb3.1 versions 1.70a and above.
Disable USB2 internal retry for the same.

Change-Id: Id476220130518c0fd740d9be5d6db1e712529112
Signed-off-by: Ajay Agarwal <quic_ajaya@quicinc.com>
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
This commit is contained in:
Ajay Agarwal 2022-01-05 12:38:49 +05:30 • committed by Udipto Goswami
commit 080a6e25a3
2 changed files with 18 additions and 1 deletions
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18
drivers/usb/dwc3/core.c
View file

@ -1157,11 +1157,27 @@ int dwc3_core_init(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_3(0),
dwc->gen2_tx_de_emph3 & DWC31_TX_DEEMPH_MASK);
/* set inter-packet gap 199.794ns to improve EL_23 margin */
/*
* Set inter-packet gap 199.794ns to improve EL_23 margin.
*
* STAR 9001346572: Host: When a Single USB 2.0 Endpoint Receives NAKs Continuously, Host
* Stops Transfers to Other Endpoints. When an active endpoint that is not currently cached
* in the host controller is chosen to be cached to the same cache index as the endpoint
* that receives NAK, The endpoint that receives the NAK responses would be in continuous
* retry mode that would prevent it from getting evicted out of the host controller cache.
* This would prevent the new endpoint to get into the endpoint cache and therefore service
* to this endpoint is not done.
* The workaround is to disable lower layer LSP retrying the USB2.0 NAKed transfer. Forcing
* this to LSP upper layer allows next EP to evict the stuck EP from cache.
*/
if (dwc->revision >= DWC3_USB31_REVISION_170A) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
reg |= DWC3_GUCTL1_IP_GAP_ADD_ON(1);
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;
dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
}
return 0;

1
drivers/usb/dwc3/core.h
View file

@ -413,6 +413,7 @@
#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
/* Global User Control Register 3 */
#define DWC3_GUCTL3_USB20_RETRY_DISABLE BIT(16)
#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
/* Device Configuration Register */