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Merge commit '6749249a5c' into remote

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Change-Id: I99148441fa13c1d725c7fff54fc648840697e031
This commit is contained in:
Naveen Kumar 2020-09-18 19:30:59 +05:30
commit 0845dc1676
63 changed files with 1882 additions and 136 deletions
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2
bindings/clock/qcom,aop-qmp.txt
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@ -7,6 +7,8 @@ Required properties :
- mboxes : list of QMP mailbox phandle and channel identifier tuples.
- mbox-names: List of identifier strings for each mailbox channel.
Must contain "qdss_clk".
- qcom,clk-stop-bimc-log: Presence indicates a BIMC logging request will
be sent to AOP during kernel panic.
Example :
clock_qdss: qcom,aopclk {

2
bindings/clock/qcom,rpmcc.txt
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@ -33,6 +33,8 @@ not containing *_A_* in the enumerator name.
Optional properties:
- qcom,hw-clk-handoff : Add this property to support initial high votes on the
to be sent to RPM as proxy votes.
- qcom,bimc-log-stop : Add this property to request RPM to stop the bimc
logging.
Example:
smd {

12
bindings/cnss/cnss-wlan.txt
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@ -69,9 +69,19 @@ Optional properties:
- qcom,mhi: phandle to indicate the device which needs MHI support.
- qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip
specifications, should be drived depending on products
- cnss-daemon-support: Boolean property to decide whether cnss_daemon
userspace QMI client is supported.
- use-nv-mac: Boolean property to indicate whether NV MAC is used or not.
- qcom,set-wlaon-pwr-ctrl: Boolean property to indicate if set
WLAON_QFPROM_PWR_CTRL_REG register during power on
and off sequences.
- use-pm-domain: Boolean property to indicate if driver needs to use PM
domain or not.
- qcom,wlan-cbc-enabled: boolean property to control cold boot calibration
- interconnects: Interconnect framework setup for bus configuration
- qcom,bus-bw-cfg-num: Number of bus bandwidth voting cases
- interconnect-names: Interconnect path names as strings
- qcom,icc-path-count: Number of Interconnect paths for this platform
- qcom,bus-bw-cfg-count: Number of bus bandwidth voting cases
- qcom,bus-bw-cfg: Bus bandwidth voting data
- qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage
regulator used in internal power amplifier for QCA6490

6
bindings/gpu/adreno.txt
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@ -198,9 +198,9 @@ Optional Properties:
baseAddr - base address of the qtimer memory region
size - size of the qtimer region
- qcom,tsens-name:
Specify the name of GPU temperature sensor. This name will be used
to get the temperature from the thermal driver API.
- qcom,tzone-names:
Specify the names of GPU thermal zones. These will be used
to get gpu temperature from the thermal driver API.
- qcom,enable-midframe-timer:
Boolean. Enables the use of midframe sampling timer. This timer

4
bindings/iio/adc/qcom,spmi-vadc.txt
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@ -83,7 +83,9 @@ Channel node properties:
fed to VADC. The configuration for this node is to know the
pre-determined ratio and use it for post scaling. Select one from
the following options.
<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>
<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>, <1 16>,
<32 100>, <14, 100>, <28, 100>, <1000 305185>, <1000 610370>
If property is not found default value depending on chip will be used.
- qcom,ratiometric:

8
bindings/input/qcom-hv-haptics.txt
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@ -112,6 +112,13 @@ Properties:
Definition: Phandle of the nvmem device used for haptics configuration.
Please refer to nvmem bindings as described in bindings/nvmem/nvmem.txt.
- qcom,pbs-client:
Usage: optional
Value type: <phandle>
Definition: Phandle of the PBS client used for triggering PBS to configure
haptics ISC (short circuit current) config during LRA impedance
detection.
The following properties are only required when LRA actuator is used:
- qcom,lra-period-us:
@ -262,6 +269,7 @@ Example:
nvmem-cells = <&hap_cl_brake>;
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8350_sdam_46>;
qcom,pbs-client = <&pm8350b_pbs2>;
qcom,vmax-mv = <900>;
qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;

318
bindings/leds/backlight/qcom-spmi-wled.txt Normal file
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@ -0,0 +1,318 @@
Bindings for Qualcomm Technologies, Inc. WLED driver
WLED (White Light Emitting Diode) driver is used for controlling display
backlight that is part of PMIC on Qualcomm Technologies, Inc. reference
platforms. The PMIC is connected to the host processor via SPMI bus.
- compatible
Usage: required
Value type: <string>
Definition: should be one of the below.
"qcom,pmi8998-spmi-wled",
"qcom,pm8150l-spmi-wled",
"qcom,pm6150l-spmi-wled"
"qcom,pm660l-spmi-wled"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Base address and size of the WLED modules.
- reg-names
Usage: required
Value type: <string>
Definition: Names associated with base addresses. should be
"wled-ctrl-base", "wled-sink-base".
- interrupts
Usage: optional
Value type: <prop encoded array>
Definition: Interrupts associated with WLED. Interrupts can be
specified as per the encoding listed under
Documentation/devicetree/bindings/spmi/
qcom,spmi-pmic-arb.txt.
- interrupt-names
Usage: optional
Value type: <string>
Definition: Interrupt names associated with the interrupts.
Currently supported interrupts are "sc-irq", "ovp-irq",
"pre-flash-irq" and "flash-irq". Pre_flash and flash
interrupts can be specified only for PMICs that has WLED5.
- label
Usage: required
Value type: <string>
Definition: The name of the backlight device.
- default-brightness
Usage: optional
Value type: <u32>
Definition: Brightness value on boot. Default is 2048.
Range of values are:
For pmi8998, it is 0-4095.
For pm8150l, this can vary from 0-4095 or 0-32767 depending
on the brightness control mode. If CABC is enabled, 0-4095
range is used.
- max-brightness
Usage: optional
Value type: <u32>
Definition: Maximum brightness level. Allowed values are:
For pmi8998, it is 4095.
For pm8150l, this can be either 4095 or 32767.
If CABC is enabled, this is capped to 4095.
- qcom,fs-current-limit
Usage: optional
Value type: <u32>
Definition: per-string full scale current limit in uA. value from
0 to 30000 with 5000 uA resolution. Default: 25000 uA
- qcom,boost-current-limit
Usage: optional
Value type: <u32>
Definition: ILIM threshold in mA. values are 105, 280, 450, 620, 970,
1150, 1300, 1500. Default: 970 mA
- qcom,switching-freq
Usage: optional
Value type: <u32>
Definition: Switching frequency in KHz. values are
600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371,
1600, 1920, 2400, 3200, 4800, 9600.
Default: 800 KHz
- qcom,ovp
Usage: optional
Value type: <u32>
Definition: Over-voltage protection limit in mV. values are 31100,
29600, 19600, 18100.
Default: 29600 mV
- qcom,string-cfg
Usage: optional
Value type: <u32>
Definition: Bit mask of the WLED strings. Bit 0 to 3 indicates strings
0 to 3 respectively. WLED module has four strings of leds
numbered from 0 to 3. Each string of leds are operated
individually. Specify the strings using the bit mask. Any
combination of led strings can be used.
Default value is 15 (b1111).
- qcom,en-cabc
Usage: optional
Value type: <bool>
Definition: Specify if cabc (content adaptive backlight control) is
needed.
- qcom,ext-pfet-sc-pro-en
Usage: optional
Value type: <bool>
Definition: Specify if external PFET control for short circuit
protection is needed. This is not applicable for PM8150L.
- qcom,auto-calibration
Usage: optional
Value type: <bool>
Definition: Enables auto-calibration of the WLED sink configuration.
- qcom,modulator-sel
Usage: optional
Value type: <u32>
Definition: Selects the modulator used for brightness modulation.
Allowed values are:
0 - Modulator A
1 - Modulator B
If not specified, then modulator A will be used by default.
This property is applicable only to WLED5 peripheral.
- qcom,cabc-sel
Usage: optional
Value type: <u32>
Definition: Selects the CABC pin signal used for brightness modulation.
Allowed values are:
0 - CABC disabled
1 - CABC 1
2 - CABC 2
3 - External signal (e.g. LPG) is used for dimming
This property is applicable only to WLED5 peripheral.
- qcom,leds-per-string
Usage: optional
Value type: <u32>
Definition: If specified, can be used to calculate available current
during selfie flash operation. If not specified, available
current calculated is simply the configured threshold.
- io-channels
Usage: optional
Value type: <phandle-array>
Definition: IIO channel specifiers for each name in io-channel-names.
- io-channel-names
Usage: optional
Value type: <string-array>
Definition: Names of the IIO channels that are used by WLED.
For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
Following properties are for child subnodes that are needed for WLED preflash
(or torch), flash and switch. These child subnodes can be specified only for
PMICs that has WLED5 (e.g. PM8150L).
For wled_torch child subnode,
- label
Usage: required
Value type: <string>
Definition: Should be "torch".
- qcom,default-led-trigger
Usage: optional
Value type: <string>
Definition: Name for LED trigger. If unspecified, "wled_torch" is used.
- qcom,wled-torch-fsc
Usage: optional
Value type: <u32>
Definition: WLED torch full scale current in mA. This configures the
maximum current allowed for torch device. Allowed values
are from 5 to 60 mA with a step of 5 mA. If not specified,
default value is set to 30 mA.
- qcom,wled-torch-step
Usage: optional
Value type: <u32>
Definition: WLED torch step delay in us. This configures the step delay
when the output is ramped up to the desired target current.
Allowed values are from 50 to 400 us with a step of 50 us.
If not specified, default value is set to 200 us.
- qcom,wled-torch-timer
Usage: optional
Value type: <u32>
Definition: WLED torch safety timer in ms. This configures the safety
timer to turn off torch automatically after timer expiry.
Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and
1200. If not specified, default value is set to 1200 ms.
For wled_flash child subnode,
- label
Usage: required
Value type: <string>
Definition: Should be "flash".
- qcom,default-led-trigger
Usage: optional
Value type: <string>
Definition: Name for LED trigger. If unspecified, "wled_flash" is used.
- qcom,wled-flash-fsc
Usage: optional
Value type: <u32>
Definition: WLED flash full scale current in mA. This configures the
maximum current allowed for flash device. Allowed values
are from 5 to 60 mA with a step of 5 mA. If not specified,
default value is set to 40 mA.
- qcom,wled-flash-step
Usage: optional
Value type: <u32>
Definition: WLED flash step delay in us. This configures the step delay
when the output is ramped up to the desired target current.
Allowed values are from 50 to 400 us with a step of 50 us.
If not specified, default value is set to 200 us.
- qcom,wled-flash-timer
Usage: optional
Value type: <u32>
Definition: WLED flash safety timer in ms. This configures the safety
timer to turn off flash automatically after timer expiry.
Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and
1200. If not specified, default value is set to 100 ms.
For wled_switch child subnode,
- label
Usage: required
Value type: <string>
Definition: Should be "switch".
- qcom,default-led-trigger
Usage: optional
Value type: <string>
Definition: Name for LED trigger. If unspecified, "wled_switch" is
used.
Example:
qcom-wled@d800 {
compatible = "qcom,pmi8998-spmi-wled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xd800 0xd900>;
reg-names = "wled-ctrl-base", "wled-sink-base";
label = "backlight";
interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sc-irq", "ovp-irq";
qcom,fs-current-limit = <25000>;
qcom,boost-current-limit = <970>;
qcom,switching-freq = <800>;
qcom,ovp = <29600>;
qcom,string-cfg = <15>;
};
qcom-wled@d800 {
compatible = "qcom,pm8150l-spmi-wled";
#address-cells = <2>;
#size-cells = <0>;
reg = <0xd800 0x100>, <0xd900 0x100>;
reg-names = "wled-ctrl-base", "wled-sink-base";
label = "backlight";
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp-irq";
qcom,string-cfg = <7>;
io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>;
io-channel-names = "rbatt",
"voltage_ocv",
"current_now";
wled_torch: qcom,wled-torch {
label = "torch";
qcom,wled-torch-fsc = <40>;
qcom,wled-torch-step = <300>;
qcom,wled-torch-timer = <600>;
};
wled_flash: qcom,wled-flash {
label = "flash";
qcom,wled-flash-fsc = <60>;
qcom,wled-flash-step = <100>;
qcom,wled-flash-timer = <200>;
};
wled_switch: qcom,wled-switch {
label = "switch";
};
};
qcom,leds@d800 {
compatible = "qcom,pm660l-spmi-wled";
reg = <0xd800 0x100>,
<0xd900 0x100>;
reg-names = "qpnp-wled-ctrl-base",
"qpnp-wled-sink-base";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp-irq";
linux,name = "wled";
linux,default-led-trigger = "bkl-trigger";
};

334
bindings/power/supply/qcom/qpnp-smblite.txt Normal file
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@ -0,0 +1,334 @@
Qualcomm Technologies, Inc. SMBLITE Charger Specific Bindings
SMBLITE Charger is an efficient programmable battery charger capable of charging a
lithium-ion battery over micro-USB or USB Type-C.
=======================
Required Node Structure
=======================
SMBLITE Charger must be described in two levels of devices nodes.
===================================
First Level Node - SMBLITE Charger
===================================
Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,qpnp-smblite".
- qcom,pmic-revid
Usage: required
Value type: phandle
Definition: Should specify the phandle of PMI's revid module. This is used to
identify the PMI subtype.
- io-channels
- io-channel-names
Usage: optional
Value type: <phandle>
Definition: For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- qcom,batteryless-platform
Usage: optional
Value type: <empty>
Definition: Boolean flag which indicates that the platform does not have a
battery, and therefore charging should be disabled. In
addition battery properties will be faked such that the device
assumes normal operation.
- qcom,fcc-max-ua
Usage: optional
Value type: <u32>
Definition: Specifies the maximum fast charge current in micro-amps in
battery profile.
If the value is not present, 1Amp is used as default.
- qcom,fv-max-uv
Usage: optional
Value type: <u32>
Definition: Specifies the maximum float voltage in micro-volts in
battery profile.
If the value is not present, 4.35V is used as default.
- qcom,usb-icl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the USB input current limit in micro-amps.
If the value is not present, 1.5Amps is used as default.
- qcom,thermal-mitigation
Usage: optional
Value type: Array of <u32>
Definition: Array of fast charge current limit values for
different system thermal mitigation levels.
This should be a flat array that denotes the
maximum charge current in mA for each thermal
level.
- qcom,chg-inhibit-threshold-mv
Usage: optional
Value type: <u32>
Definition: Charge inhibit threshold in milli-volts. Charging will be
inhibited when the battery voltage is within this threshold
from Vfloat at charger insertion. If this is not specified
then charge inhibit will be disabled by default.
Allowed values are: 50, 100, 200, 300.
- qcom,chg-term-src
Usage: optional
Value type: <u32>
Definition: Specify either the ADC or analog comparators to be used in order
to set threshold values for charge termination current.
0 - Unspecified
1 - Select ADC comparator
2 - Select ANALOG comparator
- qcom,chg-term-current-ma
Usage: optional
Value type: <u32>
Definition: When ADC comparator is selected as qcom,chg-term-src, this
parameter should be set to the desired upper threshold.
- qcom,chg-term-base-current-ma
Usage: optional
Value type: <u32>
Definition: When ADC comparator is selected as qcom,chg-term-src, this
parameter should be set to the desired lower threshold.
- qcom,auto-recharge-soc
Usage: optional
Value type: <u32>
Definition: Specifies the SOC threshold at which the charger will
restart charging after termination. The value specified
ranges from 0 - 100. The feature is enabled if this
property is specified with a valid SOC value.
- qcom,auto-recharge-vbat-mv
Usage: optional
Value type: <u32>
Definition: Specifies the battery voltage threshold at which the charger
will restart charging after termination. The value specified
is in milli-volts.
- qcom,suspend-input-on-debug-batt
Usage: optional
Value type: <empty>
Definition: Boolean flag which when present enables input suspend for
debug battery.
- qcom,fake-chg-status-on-debug-batt
Usage: optional
Value type: <empty>
Definition: Boolean flag which when present shows charging status as
unknown for debug battery. This needs to be specified only if
the device needs to be kept powered on always with
"svc power stayon true".
- qcom,typec-legacy-rp-icl
Usage: optional
Value type: bool
Definition: Boolean property to enable setting ICL based on Rp for
Type-C non-compliant legacy cables.
- qcom,wd-bark-time-secs
Usage: optional
Value type: <u32>
Definition: WD bark-timeout in seconds. The possible values are
16, 32, 64, 128. If not defined it defaults to 64.
- qcom,battery-data
Usage: optional
Value type: <phandle>
Definition: Specifies the phandle of the node which contains the battery
profiles supported on the device.
- qcom,flash-derating-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold in percentage below which hardware will start
derating flash. This is only applicable to certain PMICs like
PMI632 which has SCHGM_FLASH peripheral.
- qcom,flash-disable-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold in percentage below which hardware will disable
flash. This is only applicable to certain PMICs like PMI632
which has SCHGM_FLASH peripheral.
- qcom,headroom-mode
Usage: optional
Value type: <u32>
Definition: Specifies flash hardware headroom management policy. The
possible values are:
<0>: Fixed mode, constant 5V at flash input.
<1>: Adaptive mode allows charger output voltage to be
dynamically controlled by the flash module based on the
required flash headroom.
This is only applicable to certain PMICs like PMI632 which
has SCHGM_FLASH peripheral.
- qcom,fcc-stepping-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables stepwise change in FCC.
The default stepping rate is 100mA/sec.
- qcom,disable-suspend-on-collapse
Usage: optional
Value type: bool
Definition: Boolean flag which when present disables suspend on collapse
feature of charger hardware.
- qcom,fcc-step-delay-ms
Usage: optional
Value type: <u32>
Definition: Specifies the delay between each step of FCC stepper algorithm.
If left unspecified, the default value is 1 Sec.
- qcom,fcc-step-size-ua
Usage: optional
Value type: <u32>
Definition: Specifies the step size of each step of FCC stepper algorithm.
If left unspecified, the default value is 100mA.
=================================================
Second Level Nodes - SMBLITE Charger Peripherals
=================================================
Peripheral specific properties:
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Address and size of the peripheral's register block.
- interrupts
Usage: required
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier.
- interrupt-names
Usage: required
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property.
=======
Example
=======
pm2250_charger: qcom,qpnp-smblite {
compatible = "qcom,qpnp-smblite";
#address-cells = <1>;
#size-cells = <1>;
#cooling-cells = <2>;
qcom,pmic-revid = <&pm2250_revid>;
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts =
<0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "chgr-error",
"chg-state-change",
"buck-oc",
"vph-ov";
};
qcom,dcdc@1100 {
reg = <0x1100 0x100>;
interrupts =
<0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "otg-fail",
"otg-fault",
"skip-mode",
"input-current-limiting",
"switcher-power-ok";
};
qcom,batif@1200 {
reg = <0x1200 0x100>;
interrupts =
<0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "bat-temp",
"bat-therm-or-id-missing",
"bat-low",
"bat-ov",
"bsm-active";
};
qcom,usb@1300 {
reg = <0x1300 0x100>;
interrupts =
<0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usbin-plugin",
"usbin-collapse",
"usbin-uv",
"usbin-ov",
"usbin-gtvt",
"usbin-icl-change";
};
qcom,typec@1500 {
reg = <0x1500 0x100>;
interrupts =
<0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "typec-or-rid-detect-change",
"typec-vpd-detect",
"typec-cc-state-change",
"typec-vbus-change",
"typec-attach-detach",
"typec-legacy-cable-detect",
"typec-try-snk-src-detect";
};
qcom,misc@1600 {
reg = <0x1600 0x100>;
interrupts =
<0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "wdog-snarl",
"wdog-bark",
"aicl-fail",
"aicl-done",
"imp-trigger",
"all-chnl-cond-done",
"temp-change";
};
};

21
bindings/power/supply/qcom/smb1398-charger.txt
View file

@ -43,16 +43,19 @@ Charger specific properties:
required when SMB1396 working as a DIV2 CP master.
- io-channels
- io-channel-names
Usage: optional
Value type: <phandle>
Definition: The IIO channel for measuring SMB1398 die temperature,
io-channel-names should be "die-temp". For other details about
IIO bindings see:
Value type: <phandle-array>
Definition: IIO channel specifiers for each name in io-channel-names.
For other details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
These properties are required when SMB1396 working as a DIV2 CP
master.
- io-channel-names
Usage: optional
Value type: <string-array>
Definition: Names of the IIO channels that are used by CP master.
- qcom,div2-cp-min-ilim-ua
Usage: optional
Value type: <u32>
@ -86,8 +89,12 @@ smb1398_charger: qcom,combo_charger {
interrupt-parent = <&smb1398>;
status = "disabled";
io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
io-channel-names = "die_temp";
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_vadc ADC5_AMUX_THM2>;
io-channel-names = "current_capability",
"real_type",
"die_temp";
interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>,
<0x26 0x3 IRQ_TYPE_EDGE_RISING>,

3
bindings/regulator/gdsc-regulator.txt
View file

@ -55,6 +55,9 @@ Optional properties:
- reset-names: reset signal name strings sorted in the same order as the resets
property. These can be supplied only if we support
qcom,skip-logic-collapse.
- qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement
to leave the GDSC on that has been
enabled by an entity external to HLOS.
Example:
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {

6
bindings/reserved-memory/ramoops.txt
View file

@ -45,6 +45,12 @@ Optional properties:
- unbuffered: if present, use unbuffered mappings to map the reserved region
(defaults to buffered mappings)
- mem-type: determine the memory type of the reserved region, compatible with
<unbuffered>, 0: writecombine(same as <unbuffered> is not set), 1: noncached
(same as <unbuffered> is set), 2: normal memory(fully cached for better
performance)
(defaults to 0: writecombine)
- no-dump-oops: if present, only dump panics (defaults to panics and oops)
- flags: if present, pass ramoops behavioral flags (defaults to 0,

31
bindings/soc/qcom/qcom,rimps-log.yaml Normal file
View file

@ -0,0 +1,31 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps-log.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Rimps Logging
description: |
RIMPS logging is a device that uses mailbox to collect the logs
generated from rimps, and dump them into a dedicated log buffer
through ipc_logging framework.
An instance of rimps-log should have the mailbox controller phandle and
addresses of log buffer set aside for this purpose.
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,rimps-log"
example:
- |
rimps_log: qcom,rimps_log@fd04780 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps-log";
reg = <0x0fd04580 0x200>,
<0x0fd04780 0x200>;
mboxes = <&rimps 1>;
};

80
bindings/soc/qcom/qcom,rimps-memlat.txt Normal file
View file

@ -0,0 +1,80 @@
RIMPS memory latency
RIMPS memlat is a device that represents the use of the PMU in ARM cores
to measure the parameters for latency driven memory access patterns in rimps.
Required structure:
An instance of rimps-memlat must be described in two levels of device nodes.
The first level describes the controller while the second level describes the
monitors that the controller manages. At least one monitor is required per
controller.
[First Level Nodes]
Required properties:
- compatible: Must be "qcom,rimps-memlat-cpugrp"
- qcom,cpulist: List of CPU phandles to be monitored in a
cluster. Must be a superset of cpulists
described in second level nodes.
- reg-names: pmu-base addresses need to store the pmu events
during LPM and hotplug scenario.
[Second Level Nodes]
Required properties:
- compatible: Must be "qcom,rimps-memlat-mon-l3"
- qcom,core-dev-table: A mapping table of core frequency to a required
bandwidth vote at the given core frequency.
A phandle that contains this property may be
provided instead (to share tables across nodes).
- qcom,cachemiss-ev: The cache miss event that this monitor is
supposed to measure. Optional for compute only.
- reg-names: ftbl_base address required to populate
L3 frequency and perf_base address required to know the current
L3 frequency set.
Optional properties:
- qcom,cpulist: List of CPU phandles to be monitored in a
cluster. Must be a subset of the cpulist
described in first level node. Defaults to
cpulist in first level node if not specified.
- qcom,inst-ev: The instruction count event that this monitor is
supposed to measure. Defaults to 0x08 if not
specified.
- qcom,stall-cycle-ev: The stall cycle count that this monitor is
supposed to measure. Assumes 100% stall if not
specified.
Example:
cpu0_grp: qcom,cpu0_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x0fd04900 0x1000>;
reg-names = "pmu-base";
cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cachemiss-ev = <0x17>;
reg = <0x18590100 0xa0>, <0x18590320 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 300000 300000000 >,
< 403200 403200000 >,
< 499200 499200000 >,
< 691200 614400000 >,
< 806400 710400000 >,
< 998400 806400000 >,
< 1190400 998400000 >,
< 1286400 1094400000 >,
< 1459200 1248000000 >,
< 1728000 1344000000 >,
< 1804800 1440000000 >,
< 1900800 1516800000 >;
};
};

28
bindings/soc/qcom/qcom,rimps.yaml Normal file
View file

@ -0,0 +1,28 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Rimps Mailbox controller driver
description: |
This mailbox controller act as interface to do doorbell between
HLOS and Rimps subsystem.
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,rimps"
example:
- |
qcom,rimps@0f400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps";
reg = <0x0f400000 0x10>,
<0x0fd90000 0x2000>;
#mbox-cells = <1>;
status = "ok";
};

6
bindings/soc/qcom/qcom,secure-buffer.yaml
View file

@ -19,6 +19,12 @@ properties:
items:
- const: qcom,secure-buffer
qcom,vmid-cp-camera-preview-ro:
$ref: /schemas/types.yaml#/definitions/flag
description:
Buffers accessible to VMID_CP_CAMERA_PREVIEW must be mapped with
read-only permissions.
required:
- compatible

10
bindings/thermal/qcom-sdpm.txt
View file

@ -29,6 +29,13 @@ Properties:
Value type: <stringlist>
Definition: List of clock names matching the clock order mentioned in
the clocks property.
- <supply-name>-supply:
Usage: Optional
Value type: <regulator phandle>
Definition: phandle to the regulator device tree node that powers
this domain.
- cpu:
Usage: optional
Value type: <CPU phandle>
@ -46,9 +53,10 @@ Example:
cx_sdpm@0x00634000 {
compatible = "qcom,sdpm";
reg = <0x00634000 0x1000>;
clock-names = "cam_cc", "compo_aux";
clock-names = "cam_cc_ipe", "compo_aux";
clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
<&clk_m_a2_div1 CLK_M_COMPO_AUX>;
cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>;
cpu = <&CPU7>;
csr-id = <5 7 4>;
//CSR 5 <=> cam_cc

14
bindings/thermal/qti-isense-cdsp.txt Normal file
View file

@ -0,0 +1,14 @@
===============================================================================
QTI Limits cdsp isense driver:
===============================================================================
Limits cdsp isense driver reads cdsp isense calibration data from shared memory
and enables sysfs file support to access the data read from shared memory.
Required Parameters:
- compatible: must be 'qcom,msm-limits-cdsp' for limits cdsp isense driver.
Optional Parameters:
lmh_isense_cdsp {
compatible = "qcom,msm-limits-cdsp";
};

7
qcom/Makefile
View file

@ -14,6 +14,7 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \
lahainap-atp-overlay.dtbo \
lahainap-qrd-overlay.dtbo \
lahaina-cdp-v2.2-overlay.dtbo \
lahaina-mtp-v2-overlay.dtbo \
lahaina-mtp-v2.1-overlay.dtbo
lahaina-rumi-overlay.dtbo-base := lahaina.dtb
@ -31,6 +32,8 @@ lahainap-atp-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb
lahainap-qrd-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb
lahaina-cdp-v2.2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \
lahaina-v2.1.dtb
lahaina-mtp-v2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \
lahaina-v2.1.dtb
lahaina-mtp-v2.1-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \
lahaina-v2.1.dtb
else
@ -68,6 +71,7 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \
lahainap-v2.1-cdp.dtb \
lahainap-v2.1-atp.dtb \
lahainap-v2.1-qrd.dtb \
lahaina-mtp-v2.dtb \
lahaina-mtp-v2.1.dtb
endif
@ -75,6 +79,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
holi-mtp-overlay.dtbo \
holi-cdp-overlay.dtbo \
holi-cdp-lcd-overlay.dtbo \
holi-qrd-overlay.dtbo \
holi-atp-overlay.dtbo \
holi-mtp-usbc-overlay.dtbo
@ -82,6 +87,7 @@ dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
holi-rumi-overlay.dtbo-base := holi.dtb
holi-mtp-overlay.dtbo-base := holi.dtb
holi-cdp-overlay.dtbo-base := holi.dtb
holi-cdp-lcd-overlay.dtbo-base := holi.dtb
holi-qrd-overlay.dtbo-base := holi.dtb
holi-atp-overlay.dtbo-base := holi.dtb
holi-mtp-usbc-overlay.dtbo-base := holi.dtb
@ -89,6 +95,7 @@ else
dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \
holi-mtp.dtb \
holi-cdp.dtb \
holi-cdp-lcd.dtb \
holi-qrd.dtb \
holi-atp.dtb \
holi-mtp-usbc.dtb

5
qcom/holi-audio-overlay.dtsi
View file

@ -231,6 +231,7 @@
&holi_snd {
qcom,model = "holi-mtp-snd-card";
qcom,sku-model = "holi-mtpsku1-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
qcom,wcn-btfm = <1>;
qcom,tdm-max-slots = <4>;
@ -279,6 +280,10 @@
qcom,msm-mbhc-gnd-swh = <1>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd937x_codec>, <&wsa881x_i2c_e>,
<&wsa881x_i2c_f>;

16
qcom/holi-cdp-lcd-overlay.dts Normal file
View file

@ -0,0 +1,16 @@
/dts-v1/;
/plugin/;
#include "holi-cdp-lcd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi CDP-LCD attached";
compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp";
qcom,msm-id = <454 0x10000>, <472 0x10000>;
qcom,board-id = <1 1>;
};
&wsa881x_analog_reset_gpio {
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
};

10
qcom/holi-cdp-lcd.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "holi.dtsi"
#include "holi-cdp-lcd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi CDP-LCD attach";
compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp";
qcom,board-id = <1 1>;
};

16
qcom/holi-cdp-lcd.dtsi Normal file
View file

@ -0,0 +1,16 @@
#include "holi-cdp.dtsi"
&pm6150a_amoled {
status = "disabled";
};
&pm6150l_lcdb {
status = "ok"
};
&pm6150l_wled {
status = "ok"
qcom,string-cfg = <15>;
qcom,leds-per-string = <4>;
};

4
qcom/holi-coresight.dtsi
View file

@ -353,13 +353,13 @@
};
};
tpdm_acptm: tpdm@9860000 {
tpdm_actpm: tpdm@9860000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb968>;
reg = <0x9860000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-acptm";
coresight-name = "coresight-tpdm-actpm";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";

11
qcom/holi-gpu.dtsi
View file

@ -25,8 +25,8 @@ msm_gpu: qcom,kgsl-3d0@5900000 {
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>;
clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
"iface_clk", "mem_iface_clk", "gmu_clk";
clock-names = "core_clk", "rbbmtimer_clk", "iface_clk",
"ahb_clk", "mem_clk", "gmu_clk";
vddcx-supply = <&gpu_cx_gdsc>;
vdd-supply = <&gpu_gx_gdsc>;
@ -314,6 +314,13 @@ msm_gpu: qcom,kgsl-3d0@5900000 {
vddcx-supply = <&gpu_cx_gdsc>;
clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
clock-names = "gcc_bimc_gpu_axi", "gpu_cc_ahb",
"gcc_gpu_memnoc_gfx";
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x0>;

95
qcom/holi-mtp-usbc.dtsi
View file

@ -128,7 +128,15 @@
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>,
<&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>,
<&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>,
<&smb1396_div2_cp_master PSY_IIO_MIN_ICL>,
<&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ILIM>,
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>,
<&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
@ -152,7 +160,15 @@
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
"time_to_full_now",
"parallel_mode",
"parallel_output_mode",
"min_icl",
"cp_switcher_en",
"cp_enable",
"cp_ilim",
"cp_die_temp",
"current_capability";
qcom,battery-data = <&mtp_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
@ -177,13 +193,15 @@
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
<&pm7250b_charger PSY_IIO_CHARGE_DONE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
"charge_done",
"cp_charging_enabled";
qcom,battery-data = <&mtp_batterydata>;
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
@ -212,6 +230,75 @@
};
};
&pm7250b_vadc {
smb1390_therm@e {
qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
};
};
&pm7250b_gpios {
smb_stat {
smb_stat_default: smb_stat_default {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
power-source = <0>;
};
};
};
&qupv3_se10_i2c {
qcom,clk-freq-out = <100000>;
status = "ok"
#include "smb1398.dtsi"
};
&smb1396 {
interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&spmi_bus>;
interrupt-names = "smb1396";
pinctrl-names = "default";
qcom,enable-toggle-stat;
pinctrl-0 = <&smb_stat_default>;
status = "ok"
};
&smb1396_div2_cp_master {
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>,
<&pm7250b_vadc ADC5_AMUX_THM2>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>,
<&pm7250b_charger PSY_IIO_SMB_EN_MODE>,
<&pm7250b_charger PSY_IIO_SMB_EN_REASON>;
io-channel-names = "current_capability",
"cp_enable",
"cp_input_current_max",
"die_temp",
"real_type",
"adapter_cc_mode",
"pd_current_max",
"input_current_settled",
"smb_en_mode",
"smb_en_reason";
qcom,parallel-input-mode = <1>; /* USBIN */
qcom,parallel-output-mode = <2>; /* VBAT */
status = "ok"
};
&smb1396_slave {
status = "ok"
};
&smb1396_div2_cp_slave {
status = "ok"
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;

95
qcom/holi-mtp.dtsi
View file

@ -185,7 +185,15 @@
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>,
<&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>,
<&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>,
<&smb1396_div2_cp_master PSY_IIO_MIN_ICL>,
<&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ILIM>,
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>,
<&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
@ -209,7 +217,15 @@
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
"time_to_full_now",
"parallel_mode",
"parallel_output_mode",
"min_icl",
"cp_switcher_en",
"cp_enable",
"cp_ilim",
"cp_die_temp",
"current_capability";
qcom,battery-data = <&mtp_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
@ -234,13 +250,15 @@
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
<&pm7250b_charger PSY_IIO_CHARGE_DONE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
"charge_done",
"cp_charging_enabled";
qcom,battery-data = <&mtp_batterydata>;
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
@ -253,6 +271,75 @@
qcom,use-cp-iin-sns;
};
&pm7250b_vadc {
smb1390_therm@e {
qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
};
};
&pm7250b_gpios {
smb_stat {
smb_stat_default: smb_stat_default {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
power-source = <0>;
};
};
};
&qupv3_se10_i2c {
qcom,clk-freq-out = <100000>;
status = "ok"
#include "smb1398.dtsi"
};
&smb1396 {
interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&spmi_bus>;
interrupt-names = "smb1396";
pinctrl-names = "default";
qcom,enable-toggle-stat;
pinctrl-0 = <&smb_stat_default>;
status = "ok"
};
&smb1396_div2_cp_master {
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>,
<&pm7250b_vadc ADC5_AMUX_THM2>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>,
<&pm7250b_charger PSY_IIO_SMB_EN_MODE>,
<&pm7250b_charger PSY_IIO_SMB_EN_REASON>;
io-channel-names = "current_capability",
"cp_enable",
"cp_input_current_max",
"die_temp",
"real_type",
"adapter_cc_mode",
"pd_current_max",
"input_current_settled",
"smb_en_mode",
"smb_en_reason";
qcom,parallel-input-mode = <1>; /* USBIN */
qcom,parallel-output-mode = <2>; /* VBAT */
status = "ok"
};
&smb1396_slave {
status = "ok"
};
&smb1396_div2_cp_slave {
status = "ok"
};
#include "camera/holi-camera-sensor-mtp.dtsi"
&pm7250b_charger {

96
qcom/holi-qrd.dtsi
View file

@ -146,6 +146,7 @@
&holi_snd {
qcom,model = "holi-qrd-snd-card";
qcom,sku-model = "holi-qrdsku1-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
qcom,wcn-btfm = <1>;
qcom,audio-routing =
@ -259,7 +260,15 @@
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>,
<&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>,
<&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>,
<&smb1396_div2_cp_master PSY_IIO_MIN_ICL>,
<&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ILIM>,
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>,
<&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
@ -283,7 +292,15 @@
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
"time_to_full_now",
"parallel_mode",
"parallel_output_mode",
"min_icl",
"cp_switcher_en",
"cp_enable",
"cp_ilim",
"cp_die_temp",
"current_capability";
qcom,battery-data = <&qrd_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
@ -311,13 +328,15 @@
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
<&pm7250b_charger PSY_IIO_CHARGE_DONE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
"charge_done",
"cp_charging_enabled";
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
@ -380,3 +399,72 @@
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};
&pm7250b_vadc {
smb1390_therm@e {
qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
};
};
&pm7250b_gpios {
smb_stat {
smb_stat_default: smb_stat_default {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
power-source = <0>;
};
};
};
&qupv3_se10_i2c {
qcom,clk-freq-out = <100000>;
status = "ok"
#include "smb1398.dtsi"
};
&smb1396 {
interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&spmi_bus>;
interrupt-names = "smb1396";
pinctrl-names = "default";
qcom,enable-toggle-stat;
pinctrl-0 = <&smb_stat_default>;
status = "ok"
};
&smb1396_div2_cp_master {
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>,
<&pm7250b_vadc ADC5_AMUX_THM2>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>,
<&pm7250b_charger PSY_IIO_SMB_EN_MODE>,
<&pm7250b_charger PSY_IIO_SMB_EN_REASON>;
io-channel-names = "current_capability",
"cp_enable",
"cp_input_current_max",
"die_temp",
"real_type",
"adapter_cc_mode",
"pd_current_max",
"input_current_settled",
"smb_en_mode",
"smb_en_reason";
qcom,parallel-input-mode = <1>; /* USBIN */
qcom,parallel-output-mode = <2>; /* VBAT */
status = "ok"
};
&smb1396_slave {
status = "ok"
};
&smb1396_div2_cp_slave {
status = "ok"
};

65
qcom/holi.dtsi
View file

@ -315,11 +315,6 @@
reg = <0x0 0xc0000000 0x0 0x5100000>;
};
pil_trustedvm_mem: pil_trustedvm_region@d0000000 {
no-map;
reg = <0x0 0xd0000000 0x0 0xa600000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
@ -386,6 +381,14 @@
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
};
soc: soc { };
@ -835,6 +838,11 @@
qcom,dump-id = <0x104>;
};
osm_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x163>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
@ -910,6 +918,12 @@
qcom,rtb-size = <0x100000>;
};
qcom,mpm2-sleep-counter@0x4403000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x4403000 0x1000>;
clock-frequency = <32768>;
};
wdog: qcom,wdt@f410000 {
compatible = "qcom,msm-watchdog";
reg = <0xf410000 0x1000>;
@ -1044,6 +1058,7 @@
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
memory-region = <&memshare_mem>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
@ -1156,6 +1171,7 @@
rpmcc: clock-controller {
compatible = "qcom,rpmcc-holi";
qcom,bimc-log-stop;
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -1243,6 +1259,13 @@
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug@0fd91000 {
compatible = "qcom,cpufreq-hw-epss-debug";
reg = <0x0fd91000 0x800>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
};
ddr_bw_opp_table: ddr-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
@ -2204,7 +2227,20 @@
non-removable;
supports-cqe;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
status = "disabled";
qos0 {
mask = <0x3f>;
vote = <61>;
};
qos1 {
mask = <0xc0>;
vote = <67>;
};
};
sdhc_2: sdhci@4784000 {
@ -2251,7 +2287,19 @@
iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "bypass";
qcom,devfreq,freq-table = <50000000 202000000>;
status = "disabled";
qos0 {
mask = <0x3f>;
vote = <61>;
};
qos1 {
mask = <0xc0>;
vote = <67>;
};
};
qcom,lpass@a400000 {
@ -2710,14 +2758,17 @@
};
feat_conf8: feat_conf8@6024 {
reg = <0x6024 0x2>;
bits = <21 1>;
reg = <0x6024 0x4>;
};
gpu_gaming_bin: gpu_gaming_bin@6026 {
reg = <0x6026 0x1>;
bits = <5 1>;
};
feat_conf9: feat_conf9@6028 {
reg = <0x6028 0x4>;
};
};
};

2
qcom/lahaina-gpu.dtsi
View file

@ -51,6 +51,8 @@
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";

10
qcom/lahaina-mtp-v2-overlay.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
/plugin/;
#include "lahaina-mtp-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina MTP v2";
compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp";
qcom,board-id = <0x20008 0>;
};

10
qcom/lahaina-mtp-v2.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "lahaina-v2.dtsi"
#include "lahaina-mtp-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina MTP v2";
compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp";
qcom,board-id = <0x20008 0>;
};

1
qcom/lahaina-mtp-v2.dtsi Normal file
View file

@ -0,0 +1 @@
#include "lahaina-mtp.dtsi"

8
qcom/lahaina-pcie.dtsi
View file

@ -336,7 +336,7 @@
qcom,slv-addr-space-size = <0x20000000>;
qcom,ep-latency = <10>;
qcom,pcie-phy-ver = <1104>;
qcom,pcie-phy-ver = <1106>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
@ -408,12 +408,16 @@
0x1978 0x5c 0x0
0x197c 0x34 0x0
0x1980 0xa6 0x0
0x10cc 0xf0 0x0
0x18cc 0xf0 0x0
0x10d8 0x0f 0x0
0x18d8 0x0f 0x0
0x10dc 0x00 0x0
0x18dc 0x00 0x0
0x11a4 0x38 0x0
0x19a4 0x38 0x0
0x0e3c 0x1d 0x0
0x163c 0x1d 0x0
0x0e40 0x0c 0x0
0x1640 0x0c 0x0
0x1190 0x34 0x0
@ -423,7 +427,7 @@
0x1050 0x08 0x0
0x1850 0x08 0x0
0x02dc 0x05 0x0
0x0388 0x88 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x03e0 0x0f 0x0
0x060c 0x1d 0x0

1
qcom/lahaina-pmic-overlay.dtsi
View file

@ -354,6 +354,7 @@
nvmem-cells = <&hap_cl_brake>;
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8350_sdam_46>;
qcom,pbs-client = <&pm8350b_pbs2>;
};
&pmr735a_tz {

6
qcom/lahaina-qrd-common.dtsi
View file

@ -205,6 +205,12 @@
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};

2
qcom/lahaina-regulators.dtsi
View file

@ -826,7 +826,7 @@
S2E: pmr735a_s2: regulator-pmr735a-s2 {
regulator-name = "pmr735a_s2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <976000>;
qcom,init-voltage = <852000>;
};

52
qcom/lahaina-thermal.dtsi
View file

@ -17,6 +17,27 @@
};
};
&soc {
mx_sdpm@0x00636000 {
compatible = "qcom,sdpm";
reg = <0x00636000 0x1000>;
clock-names = "cam_cc_ipe", "video_cc_mvs0", "gcc_gp1";
clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>,
<&clock_gcc GCC_GP1_CLK_SRC>;
cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>;
video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>;
csr-id = <1 3 5>;
};
mx_pe: mx_rdpm_pe@0x00637000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x00637000 0x1000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
};
};
&cpufreq_hw {
qcom,cpu-isolation {
compatible = "qcom,cpu-isolate";
@ -1120,5 +1141,36 @@
};
};
mx-pe-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&mx_pe>;
thermal-governor = "step_wise";
trips {
mx_pe_config1: mx-pe-config1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
mx_pe_config2: mx-pe-config2 {
temperature = <2>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
mx_pe_cdev_1 {
trip = <&mx_pe_config1>;
cooling-device = <&cdsp_sw 1 1>;
};
mx_pe_cdev_2 {
trip = <&mx_pe_config2>;
cooling-device = <&msm_gpu 1 1>;
};
};
};
};

13
qcom/lahaina-usb.dtsi
View file

@ -510,11 +510,11 @@
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xB4 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5C 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xDC 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xDC 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
@ -523,7 +523,7 @@
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x09 0
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
@ -538,9 +538,10 @@
USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0
USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0
USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0
USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0
USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0

20
qcom/lahaina-v2-gpu.dtsi
View file

@ -23,7 +23,7 @@
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0x882c5ffd>;
qcom,acd-level = <0x882a5ffd>;
};
qcom,gpu-pwrlevel@1 {
@ -39,7 +39,7 @@
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82d5ffd>;
qcom,acd-level = <0xa82a5ffd>;
};
qcom,gpu-pwrlevel@2 {
@ -55,7 +55,7 @@
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82d5ffd>;
qcom,acd-level = <0xa82a5ffd>;
};
qcom,gpu-pwrlevel@3 {
@ -71,7 +71,7 @@
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82c5ffd>;
qcom,acd-level = <0x882b5ffd>;
};
qcom,gpu-pwrlevel@4 {
@ -87,7 +87,7 @@
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0x882d5ffd>;
qcom,acd-level = <0xa82b5ffd>;
};
qcom,gpu-pwrlevel@5 {
@ -103,7 +103,7 @@
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <9>;
qcom,acd-level = <0xa82d5ffd>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@6 {
@ -118,6 +118,8 @@
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@7 {
@ -132,6 +134,8 @@
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@8 {
@ -146,6 +150,8 @@
qcom,bus-freq-ddr8 = <6>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@9 {
@ -160,6 +166,8 @@
qcom,bus-freq-ddr8 = <2>;
qcom,bus-min-ddr8 = <2>;
qcom,bus-max-ddr8 = <7>;
qcom,acd-level = <0x882f5ffd>;
};
};
};

5
qcom/lahaina-v2.1.dtsi
View file

@ -8,7 +8,7 @@
&pcie0 {
qcom,l1ss-sleep-disable = <0x0>;
qcom,pcie-phy-ver = <21100>;
qcom,pcie-phy-ver = <21101>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
@ -66,6 +66,7 @@
0x1180 0xa6 0x0
0x1190 0x34 0x0
0x10d8 0x07 0x0
0x0e3c 0x1d 0x0
0x0e40 0x0c 0x0
0x10dc 0x00 0x0
0x104c 0x08 0x0
@ -78,7 +79,7 @@
0x06a8 0x0f 0x0
0x0048 0x90 0x0
0x0620 0xc1 0x0
0x0388 0xa8 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x02dc 0x05 0x0
0x0200 0x00 0x0

17
qcom/lahaina-vm-cdp.dtsi
View file

@ -1 +1,18 @@
/*#include "display/lahaina-sde-display-cdp.dtsi"*/
&qupv3_se4_i2c {
status = "ok"
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,x-flip = <1>;
st,y-flip = <1>;
st,regulator_dvdd = "vdd";
st,regulator_avdd = "avdd";
st,trusted-touch-mode = "vm_mode";
st,touch-environment = "tvm";
st,trusted-touch-spi-irq = <566>;
st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};

17
qcom/lahaina-vm-mtp.dtsi
View file

@ -1 +1,18 @@
/*#include "display/lahaina-sde-display-mtp.dtsi"*/
&qupv3_se4_i2c {
status = "ok"
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,x-flip = <1>;
st,y-flip = <1>;
st,regulator_dvdd = "vdd";
st,regulator_avdd = "avdd";
st,trusted-touch-mode = "vm_mode";
st,touch-environment = "tvm";
st,trusted-touch-spi-irq = <566>;
st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};

17
qcom/lahaina-vm-qrd.dtsi
View file

@ -1 +1,18 @@
/*#include "display/lahaina-sde-display-qrd.dtsi"*/
&qupv3_se4_i2c {
status = "ok"
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>;
};

25
qcom/lahaina-vm.dtsi
View file

@ -118,7 +118,6 @@
iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1
0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1
0x0 0xc600000 0x0 0xc600000 0x0 0x2000000 0x1
0x0 0xe600000 0x0 0xe600000 0x0 0x100000 0x1
0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1
0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
@ -303,19 +302,6 @@
qcom,wrapper-core = <&qupv3_0>;
qcom,le-vm;
status = "ok"
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,x-flip = <1>;
st,y-flip = <1>;
st,regulator_dvdd = "vdd";
st,regulator_avdd = "avdd";
st,trusted-touch-mode = "vm_mode";
st,touch-environment = "tvm";
st,trusted-touch-spi-irq = <566>;
st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>;
};
};
qupv3_se4_spi: spi@990000 {
@ -332,6 +318,15 @@
qcom,le-vm;
status = "disabled";
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
qcom,support-hypervisor;
};
};
#include "lahaina-vm-ion.dtsi"
@ -339,3 +334,5 @@
#include "display/trustedvm-lahaina-sde-display.dtsi"
#include "display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
#include "display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
#include "display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
#include "display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi"

66
qcom/lahaina.dtsi
View file

@ -523,6 +523,19 @@
label = "dfps_data_region";
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
/*
* Memory shared with modem needs to be outside of
* the CLADE address space, which begins at
* 0xE0000000 and spans 512 MB.
*/
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
@ -2288,6 +2301,7 @@
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
memory-region = <&memshare_mem>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
@ -2332,8 +2346,9 @@
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clock-names = "cfg_ahb_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>;
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -2344,8 +2359,9 @@
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clock-names = "cfg_ahb_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>;
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -2355,8 +2371,9 @@
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
clock-names = "cfg_ahb_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -2735,6 +2752,7 @@
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom-mem-buf {
@ -5211,6 +5229,7 @@
qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */
qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */
qcom,spss-debug-reg-addr = <0x01886020>;
qcom,spss-scsr-regs-addr = <0x01880000>; /* SPU shared register */
qcom,spss-emul-type-reg-addr = <0x01fc8004>;
pil-mem = <&pil_spss_mem>;
qcom,pil-size = <0x0F0000>; // padding to 960 KB
@ -5325,6 +5344,7 @@
qcom,wlan-cbc-enabled;
/* RPMH_PDC_WLAN_RF_TCS<6>_CMD<2> offset */
qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>;
use-pm-domain;
vdd-wlan-aon-supply = <&S2E>;
qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
@ -5339,22 +5359,38 @@
wlan-ant-switch-supply = <&L7E>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
qcom,bus-bw-cfg-num = <7>;
interconnects =
<&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <7>;
qcom,bus-bw-cfg =
/* no vote */
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<2250 390000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<7500 390000>,
/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<30000 790000>,
/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<100000 790000>,
/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
<175000 1600000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
* ddr: 547.2 MHz
*/
<7500 390000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr freq: 451.2 MHz */
<2250 1600000>,
/* low: 18-60 Mbps ddr freq: 451.2 MHz */
<7500 1600000>,
/* medium: 60-240 Mbps ddr freq: 451.2 MHz */
<2250 1804800>,
<7500 1804800>,
<30000 1804800>,
/* high: 240 - 1080 Mbps ddr freq: 451.2 MHz */
<100000 1804800>,
/* high: 1080 - 1400 Mbps ddr freq: 451.2 MHz */
<175000 1804800>,
/* low (latency critical): 18 - 60 Mbps, ddr freq: 547.2 MHz */
<175000 6220800>,
<7500 2188800>;
mhi,max-channels = <30>;

1
qcom/msm-arm-smmu-shima.dtsi
View file

@ -340,6 +340,7 @@
};
kgsl_iommu_coherent_test_device {
status = "disabled";
compatible = "iommu-debug-test";
iommus = <&kgsl_smmu 0x407 0>;
qcom,iommu-dma = "disabled";

5
qcom/pm8350b.dtsi
View file

@ -21,6 +21,11 @@
#thermal-sensor-cells = <0>;
};
pm8350b_pbs2: qcom,pbs@1900 {
compatible = "qcom,qpnp-pbs";
reg = <0x1900>;
};
pm8350b_gpios: pinctrl@8800 {
compatible = "qcom,pm8350b-gpio";
reg = <0x8800>;

2
qcom/sdxlemur-pcie.dtsi
View file

@ -70,7 +70,7 @@
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
<&gcc GCC_PCIE_PIPE_CLK_SRC>,
<&gcc PCIE_PIPE_CLK>;
<&pcie_pipe_clk>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",

2
qcom/sdxlemur.dtsi
View file

@ -462,7 +462,7 @@
mc_virt: interconnect {
compatible = "qcom,sdxlemur-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos"
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};

4
qcom/shima-audio-overlay.dtsi
View file

@ -316,7 +316,7 @@
"wsa-codec1", "wsa-codec2";
qcom,wsa-max-devs = <2>;
qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0000429 0x0000422>;
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>;
qcom,cps_threshold_levels = <148 168>;
qcom,cps_normal_values = <0x8E 0x8F 0x8F>;
qcom,cps_lower1_values = <0x10 0xD0 0xD0>;
@ -420,5 +420,5 @@
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
adsp-fw-names = "adsp2";
adsp-fw-bit-values = <0x1>;
adsp-fw-bit-values = <0x4>;
};

4
qcom/shima-coresight.dtsi
View file

@ -107,7 +107,7 @@
coresight-name = "coresight-tmc-etf";
coresight-csr = <&swao_csr>;
coresight-ctis = <&cti0_swao &cti3_swao>;
coresight-ctis = <&cti0 &cti6>;
clocks = <&aopcc QDSS_CLK>;
clock-names = "apb_pclk";
@ -154,7 +154,7 @@
qcom,sw-usb;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti3_swao>;
coresight-ctis = <&cti0 &cti6>;
coresight-csr = <&csr>;
clocks = <&aopcc QDSS_CLK>;

4
qcom/shima-gdsc.dtsi
View file

@ -4,6 +4,8 @@
compatible = "qcom,gdsc";
reg = <0x16b004 0x4>;
regulator-name = "gcc_pcie_0_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
status = "disabled";
};
@ -11,6 +13,8 @@
compatible = "qcom,gdsc";
reg = <0x18d004 0x4>;
regulator-name = "gcc_pcie_1_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
status = "disabled";
};

11
qcom/shima-idp.dtsi
View file

@ -98,7 +98,7 @@
vdd-hba-fixed-regulator;
vcc-supply = <&L7B>;
vcc-voltage-level = <2504000 2950000>;
vcc-voltage-level = <2950000 2960000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
@ -179,7 +179,14 @@
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video
&dsi_r66451_amoled_60hz_video>;
&dsi_r66451_amoled_60hz_video
&dsi_r66451_amoled_60hz_cmd>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};

2
qcom/shima-pcie.dtsi
View file

@ -59,7 +59,7 @@
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,

4
qcom/shima-pm.dtsi
View file

@ -58,8 +58,8 @@
entry-latency-us = <3638>;
exit-latency-us = <6562>;
min-residency-us = <9826>;
arm,psci-suspend-param = <0xc240>;
qcom,psci-mode = <0xc24>;
arm,psci-suspend-param = <0xc340>;
qcom,psci-mode = <0xc34>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <2>;

3
qcom/shima-pmic-overlay.dtsi
View file

@ -495,6 +495,9 @@
&pm8350b_haptics {
nvmem-cell-names = "hap_cl_brake";
nvmem-cells = <&hap_cl_brake>;
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8350_sdam_46>;
qcom,pbs-client = <&pm8350b_pbs2>;
};
&pmr735b_tz {

33
qcom/shima-qrd.dtsi
View file

@ -4,6 +4,7 @@
#include "shima-thermal-overlay.dtsi"
#include "shima-audio-overlay.dtsi"
#include "display/shima-sde-display-qrd.dtsi"
#include "camera/shima-camera-sensor-qrd.dtsi"
&soc {
gpio_keys {
@ -79,7 +80,7 @@
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
@ -98,7 +99,7 @@
vdd-hba-fixed-regulator;
vcc-supply = <&L7B>;
vcc-voltage-level = <2504000 2950000>;
vcc-voltage-level = <2950000 2960000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
@ -220,10 +221,24 @@
};
};
&wsa883x_0221 {
status = "disabled";
};
&shima_snd {
qcom,model = "lahaina-shimaqrd-snd-card";
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"Analog Mic1", "MIC BIAS3",
"AMIC2", "Analog Mic2",
"Analog Mic2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"Analog Mic3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"Analog Mic4", "MIC BIAS1",
"AMIC5", "Analog Mic5",
"Analog Mic5", "MIC BIAS4",
"TX DMIC0", "Digital Mic0",
"Digital Mic0", "MIC BIAS1",
"TX DMIC1", "Digital Mic1",
@ -247,7 +262,6 @@
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
@ -260,8 +274,13 @@
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5";
"VA DMIC5", "Digital Mic5",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS3",
"VA DMIC2", "VA MIC BIAS4",
"VA DMIC3", "VA MIC BIAS1",
"VA DMIC4", "VA MIC BIAS3",
"VA DMIC5", "VA MIC BIAS4";
qcom,swr-dmic-max-devs = <0>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
@ -274,10 +293,10 @@
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>;
<&wsa883x_0222>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2";
"wsa-codec2";
qcom,wsa-max-devs = <1>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;

10
qcom/shima-regulators.dtsi
View file

@ -673,14 +673,17 @@
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
proxy-supply = <&pm8350c_l12>;
L12C:
pm8350c_l12: regulator-pm8350c-l12 {
regulator-name = "pm8350c_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-min-microvolt = <1920000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1620000>;
qcom,init-voltage = <1920000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-current = <60700>;
};
};
@ -692,6 +695,7 @@
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
proxy-supply = <&pm8350c_l13>;
L13C:
pm8350c_l13: regulator-pm8350c-l13 {
regulator-name = "pm8350c_l13";
@ -700,6 +704,8 @@
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-current = <30000>;
};
};

1
qcom/shima-vidc.dtsi
View file

@ -54,6 +54,7 @@
qcom,iommu-pagetable = "LLC";
buffer-types = <0xfff>;
virtual-addr-pool = <0x25800000 0xba800000>;
dma-coherent-hint-cached;
};
secure_non_pixel_cb {

15
qcom/shima-vm-ion.dtsi
View file

@ -1,15 +0,0 @@
#include <dt-bindings/arm/msm/msm_ion_ids.h>
/ {
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <1>;
#size-cells = <0>;
tui_heap: qcom,ion-heap-tui { /* TRUSTED UI CARVEOUT HEAP */
reg = <ION_TUI_CARVEOUT_HEAP_ID>;
qcom,dynamic-heap;
qcom,ion-heap-type = "MSM_CARVEOUT";
};
};
};

2
qcom/shima-vm.dtsi
View file

@ -225,4 +225,4 @@
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
};
#include "shima-vm-ion.dtsi"
#include "lahaina-vm-ion.dtsi"

280
qcom/shima.dtsi
View file

@ -33,6 +33,15 @@
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
mboxes = <&qmp_aop 0>;
};
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/
@ -403,6 +412,13 @@
size = <0x0 0x1400000>;
};
qcom: ramoops {
compatible = "ramoops";
reg = <0x0 0xa9000000 0x0 0x200000>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
@ -421,6 +437,14 @@
size = <0x0 0x400000>;
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
@ -436,10 +460,19 @@
size = <0x0 0x1C00000>;
};
splash_memory: splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_memory {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_memory";
};
};
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000";
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
soc: soc { };
@ -613,10 +646,100 @@
reg = <0x117f000 0x1000>,
<0x1112000 0x6000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
@ -676,6 +799,7 @@
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
memory-region = <&memshare_mem>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
@ -789,6 +913,7 @@
mboxes = <&qmp_aop 0>;
mbox-names = "qdss_clk";
#clock-cells = <1>;
qcom,clk-stop-bimc-log;
};
gcc: clock-controller@100000 {
@ -894,9 +1019,22 @@
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug@18591000 {
compatible = "qcom,cpufreq-hw-epss-debug";
reg = <0x18591000 0x800>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>,
<&cpufreq_hw 2>;
};
qcom_tzlog: tz-log@0x146aa720 {
compatible = "qcom,tz-log";
reg = <0x146aa720 0x3000>;
@ -1568,9 +1706,8 @@
qcom,iommu-dma = "bypass";
dma-coherent;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
rpm-level = <3>;
spm-level = <5>;
status = "disabled";
@ -1644,7 +1781,20 @@
non-removable;
supports-cqe;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <61>;
};
qos1 {
mask = <0xf0>;
vote = <67>;
};
};
sdhc_2: sdhci@8804000 {
@ -1692,7 +1842,19 @@
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 202000000>;
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <61>;
};
qos1 {
mask = <0xf0>;
vote = <67>;
};
};
apps_rsc: rsc@18200000 {
@ -1710,7 +1872,7 @@
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
<CONTROL_TCS 0>;
rpmhcc: qcom,rpmhclk {
compatible = "qcom,shima-rpmh-clk";
@ -1743,6 +1905,11 @@
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};
sde_rsc_rpmh {
compatible = "qcom,sde-rsc-rpmh";
cell-index = <0>;
};
};
spmi_bus: qcom,spmi@c440000 {
@ -1908,6 +2075,8 @@
reg = <0x9200000 0xd0000> , <0x9600000 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&aopcc QDSS_CLK>;
clock-names = "qdss_clk";
};
clk_virt: interconnect {
@ -1947,7 +2116,9 @@
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
@ -1957,9 +2128,7 @@
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
};
@ -2021,7 +2190,7 @@
llcc_bw_opp_table: llcc-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 150, 32); /* 4576 MB/s */
BW_OPP_ENTRY( 300, 32); /* 9154 MB/s */
BW_OPP_ENTRY( 300, 32); /* 9155 MB/s */
BW_OPP_ENTRY( 466, 32); /* 14220 MB/s */
BW_OPP_ENTRY( 600, 32); /* 18310 MB/s */
BW_OPP_ENTRY( 806, 32); /* 24596 MB/s */
@ -2249,7 +2418,7 @@
< 691200 556800000 >,
< 940800 652800000 >,
< 1171200 844800000 >,
< 1516800 1065600000 >,
< 1516800 1056000000 >,
< 1670400 1305600000 >,
< 1804800 1420800000 >;
};
@ -2268,7 +2437,7 @@
< 1094400 556800000 >,
< 1267200 806400000 >,
< 1766400 1190400000 >,
< 2227200 1401600000 >,
< 2169600 1401600000 >,
< 2707200 1420800000 >;
};
@ -2505,7 +2674,7 @@
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 300, 4) >,
< 2707200 MHZ_TO_MBPS(2033, 4) >;
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
@ -2558,6 +2727,8 @@
qcom,signal-aop;
qcom,complete-ramdump;
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<&modem_smp2p_in 0 0>,
@ -2612,13 +2783,15 @@
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>;
<&adsp_smp2p_in 3 0>,
<&adsp_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack";
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to lpass */
qcom,smem-states = <&adsp_smp2p_out 0>;
@ -2661,13 +2834,15 @@
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>;
<&cdsp_smp2p_in 3 0>,
<&cdsp_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack";
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
@ -3209,6 +3384,16 @@
qcom,dump-id = <0x102>;
};
LLCC_1: llcc_1_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x140>;
};
LLCC_2: llcc_2_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x141>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
@ -3224,6 +3409,11 @@
qcom,dump-id = <0x104>;
};
osm_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x163>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
@ -3261,10 +3451,13 @@
feat_conf_m7: feat_conf_m7@6020 {
reg = <0x6020 0x4>;
};
feat_conf_qc_spare_20_lsb: feat_conf_qc_spare_20_lsb@4700 {
reg = <0x4700 0x4>;
};
};
wlan: qcom,cnss-qca6490@b0000000 {
status = "disabled";
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
@ -3289,6 +3482,40 @@
wlan-ant-switch-supply = <&L11C>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
interconnects =
<&aggre1_noc MASTER_PCIE_0 &aggre1_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <7>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<2250 390000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<7500 390000>,
/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<30000 790000>,
/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<100000 790000>,
/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
<175000 1600000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
* ddr: 547.2 MHz
*/
<7500 390000>,
/** ICC Path 2 **/
<0 0>,
<2250 1804800>,
<7500 1804800>,
<30000 1804800>,
<100000 1804800>,
<175000 6220800>,
<7500 2188800>;
mhi,max-channels = <30>;
mhi,timeout = <10000>;
mhi,buffer-len = <0x8000>;
@ -3608,18 +3835,22 @@
};
&gcc_pcie_0_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_pcie_1_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_ufs_phy_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_usb30_prim_gdsc {
qcom,retain-regs;
status = "ok"
};
@ -3660,6 +3891,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3669,6 +3901,7 @@
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3677,6 +3910,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3685,6 +3919,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3693,6 +3928,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3702,6 +3938,7 @@
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3711,6 +3948,7 @@
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3719,6 +3957,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3727,6 +3966,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
vdd_parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3736,6 +3976,7 @@
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3744,6 +3985,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3753,6 +3995,7 @@
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3761,6 +4004,7 @@
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};

58
qcom/smb1398.dtsi Normal file
View file

@ -0,0 +1,58 @@
#include <dt-bindings/interrupt-controller/irq.h>
smb1396: qcom,smb1396@34 {
compatible = "qcom,i2c-pmic";
reg = <0x34>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
qcom,periph-map = <0x6 0x26 0x27>;
status = "disabled";
smb1396_div2_cp_master: qcom,div2_cp {
compatible = "qcom,smb1396-div2-cp-master";
#io-channel-cells = <1>;
interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>,
<0x26 0x3 IRQ_TYPE_EDGE_RISING>,
<0x26 0x5 IRQ_TYPE_EDGE_RISING>,
<0x26 0x7 IRQ_TYPE_EDGE_RISING>,
<0x27 0x5 IRQ_TYPE_EDGE_RISING>,
<0x27 0x6 IRQ_TYPE_EDGE_RISING>,
<0x27 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "temp-shdwn",
"div2-irev",
"usbin-uv",
"usbin-ov",
"div2-ilim",
"div2-win-uv",
"div2-win-ov";
qcom,div2-cp-min-ilim-ua = <1000000>;
status = "disabled";
};
};
smb1396_slave: qcom,smb1396@35 {
compatible = "qcom,i2c-pmic";
reg = <0x35>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
smb1396_div2_cp_slave: qcom,div2_cp_slave {
compatible = "qcom,smb1396-div2-cp-slave";
#io-channel-cells = <1>;
status = "disabled";
};
};
smb1398: qcom,smb1398@36 {
compatible = "qcom,i2c-pmic";
reg = <0x36>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
smb1398_pre_regulator: qcom,pre_regulator {
compatible = "qcom,smb1398-pre-regulator";
status = "disabled";
};
};